Improvements based on testing boot of Integrity OS in ELF format with…

… XIP. Enabled QUICC, Progress on FMAN and MP. Tab cleanups.

config/examples/nxp-t1024.config

@@ -24,6 +24,7 @@ RAM_CODE?=0
 DUALBANK_SWAP?=0
 WOLFTPM?=0
 ELF?=1
+DEBUG_ELF=0
 
 # NOR Base Address
 ARCH_FLASH_OFFSET?=0xEC000000
@@ -54,3 +55,6 @@ WOLFBOOT_DTS_BOOT_ADDRESS?=0xEC020000
 WOLFBOOT_DTS_UPDATE_ADDRESS?=0xEC040000
 # DTS Load to RAM Address
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x7F100000
+
+# Read from flash using larger chunks
+CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096

docs/Targets.md

@@ -1295,6 +1295,26 @@ make test-app/image_v1_signed.bin
 
 If getting errors with keystore then you can reset things using `make distclean`.
 
+### Signing Custom application
+
+```
+./tools/keytools/sign --ecc384 --sha384 custom.elf wolfboot_signing_private_key.der 1
+```
+
+### Assembly of custom firmware image
+
+```
+./tools/bin-assemble/bin-assemble factory_custom.bin \
+    0xEC000000 RCW_CTS.bin \
+    0xEC020000 custom.dtb \
+    0xEE000000 custom_v1_signed.bin \
+    0xEFE00000 iram_Type_A_T1024_r1.0.bin \
+    0xEFF00000 fsl_fman_ucode_t1024_r1.0_108_4_5.bin \
+    0xEFF40000 wolfboot.bin
+```
+
+Flash factory_custom.bin to NOR base 0xEC00_0000
+
 
 
 ## NXP QorIQ T2080 PPC

hal/nxp_t1024.c

@@ -26,6 +26,8 @@
 #include "nxp_ppc.h"
 
 /* Tested on T1024E Rev 1.0, e5500 core 2.1, PVR 8024_1021 and SVR 8548_0010 */
+/* IFC: CS0 NOR, CS1 MRAM, CS2 CPLD, CS3, MPU CPLD */
+/* DDR4 w/ECC (5 chips MT40A256M16GE-083EIT) - I2C1 SPD Addr 0x51 */
 
 /* Tests */
 #if 1
@@ -37,7 +39,8 @@
 #define ENABLE_DDR
 #define ENABLE_IFC
 #define ENABLE_CPLD
-//#define ENABLE_QE   /* QUICC Engine */
+#define ENABLE_QE   /* QUICC Engine */
+//#define ENABLE_FMAN
 //#define ENABLE_MP   /* multi-core support */
 #if defined(WOLFBOOT_TPM) || defined(TEST_TPM)
     #define ENABLE_ESPI /* SPI for TPM */
@@ -66,9 +69,9 @@ static int test_tpm(void);
 #define SYS_CLK (400000000) /* 400MHz */
 
 /* Boot page translation register - T1024RM 4.5.9 */
-#define LCC_BSTRH            ((volatile uint32_t*)(CCSRBAR + 0x20))
-#define LCC_BSTRL            ((volatile uint32_t*)(CCSRBAR + 0x24))
-#define LCC_BSTAR            ((volatile uint32_t*)(CCSRBAR + 0x28))
+#define LCC_BSTRH            ((volatile uint32_t*)(CCSRBAR + 0x20)) /* Boot space translation register high */
+#define LCC_BSTRL            ((volatile uint32_t*)(CCSRBAR + 0x24)) /* Boot space translation register low */
+#define LCC_BSTAR            ((volatile uint32_t*)(CCSRBAR + 0x28)) /* Boot space translation attribute register */
 #define LCC_BSTAR_EN         0x80000000
 #define LCC_BSTAR_LAWTRGT(n) ((n) << 20)
 #define LCC_BSTAR_LAWSZ(n)   ((n) & 0x3F)
@@ -151,6 +154,71 @@ static int test_tpm(void);
 #define QE_RESET               0x80000000
 
 
+/* T1024RM 10.5.1: Queue Manager (QMan):
+ * - QMan block base address: 31_8000h
+ * - 512 frame queue (FQ) cache
+ * - 2-Kbyte SFDRs
+ * - 256 congestion groups
+ */
+
+/* T1024RM 10.5.2: Buffer Manager (BMan):
+ * - BMan block base address: 31_A000h
+ * - 64 buffer pools
+ */
+
+/* T1024RM 10.5.4: Security and Encryption Engine (SEC)
+  * - SEC block base address: 30_0000h
+  * - 2.5 Gbps SEC processing at 400 MHz
+  * - Cryptographic Hardware Accelerators (CHAs) include:
+  *   - PKHA
+  *   - DESA
+  *   - AESA
+  *   - MDHA
+  *   - RNG4
+  *   - AFHA
+  */
+
+/* T1024RM 10.5.3: Frame Manager (FMan):
+  * - FMan block base address: 40_0000h
+  * - Four multirate Ethernet MACs, for configuration options refer to SerDes Protocols
+  * - Block base addresses are as follows:
+  *   - FM1 mEMAC1: 4E_0000h
+  *   - FM1 mEMAC2: 4E_2000h
+  *   - FM1 mEMAC3: 4E_4000h
+  *   - FM1 mEMAC4: 4E_6000h
+  * - mEMAC PortIDs (RX/TX):
+  *   - mEMAC1: 08h/28h
+  *   - mEMAC2: 09h/29h
+  *   - mEMAC3: 0Ah/2Ah
+  *   - mEMAC4: 0Bh/2Bh
+  * - Supports 1 host command and 3 offline ports:
+  *   - Host command: 02h
+  *   - Offline port 3: 03h
+  *   - Offline port 4: 04h
+  *   - Offline port 5: 05h
+  * - FM1 Dedicated MDIO1: 4F_C000h
+  * - FM1 Dedicated MDIO2: 4F_D000h
+  * - One FMan Controller complexes
+  * - 192-Kbyte internal FMan memory
+  * - 32-Kbyte FMan Controller configuration data
+  * - Up to 32 Keygen schemes
+  * - Up to 8 Policer profiles
+  * - Up to 32 entries in FMan DMA command queue
+  * - Up to 64 TNUMs
+  * - Up to 1 FMan debug flows
+  */
+
+#define FMAN_COUNT 1
+
+#ifndef FMAN_FW_ADDR
+#define FMAN_FW_ADDR   0xEFF00000 /* location in NOR flash */
+#endif
+
+#define FMAN_BASE              (CCSRBAR + 0x400000)
+//#define QE_CEPIER              ((volatile uint32_t*)(FMAN_BASE + 0x00CUL))
+
+
+
 /* T1024 PC16552D Dual UART */
 #define BAUD_RATE 115200
 #define UART_SEL 0 /* select UART 0 or 1 */
@@ -949,8 +1017,8 @@ static void hal_cpld_init(void)
 }
 
 
-/* ---- QUICC Engine Driver ---- */
-#ifdef ENABLE_QE
+/* QE Microcode */
+#if defined(ENABLE_QE) || defined(ENABLE_FMAN)
 
 /* Structure packing */
 #if (defined(__IAR_SYSTEMS_ICC__) && (__IAR_SYSTEMS_ICC__ > 8)) || \
@@ -1111,6 +1179,11 @@ static int qe_upload_firmware(const struct qe_firmware *firmware)
     return 0;
 }
 
+#endif
+
+/* ---- QUICC Engine Driver ---- */
+#ifdef ENABLE_QE
+
 static void qe_issue_cmd(uint32_t cmd, uint32_t sbc, uint8_t mcn,
     uint32_t cmd_data)
 {
@@ -1160,6 +1233,20 @@ static int hal_qe_init(void)
 }
 #endif /* ENABLE_QUICC */
 
+#ifdef ENABLE_FMAN
+static int hal_fman_init(void)
+{
+    int ret;
+
+    /* Upload microcode to IRAM */
+    ret = qe_upload_firmware((const struct qe_firmware *)FMAN_FW_ADDR);
+    if (ret == 0) {
+
+    }
+    return ret;
+}
+#endif /* ENABLE_FMAN */
+
 
 /* SMP Multi-Processor Driver */
 #ifdef ENABLE_MP
@@ -1172,12 +1259,13 @@ extern uint32_t _bootpg_addr;
 /* Startup additional cores with spin table and synchronize the timebase */
 static void hal_mp_up(uint32_t bootpg)
 {
-    uint32_t up, cpu_up_mask, whoami, bpcr;
+    uint32_t all_cores, active_cores, whoami, bpcr;
     uint8_t *spin_table_addr;
     int timeout = 50, i;
 
-    /* Get current running core number */
-    whoami = get32(PIC_WHOAMI);
+    whoami = get32(PIC_WHOAMI); /* Get current running core number */
+    all_cores = ((1 << CPU_NUMCORES) - 1); /* mask of all cores */
+    active_cores = (1 << whoami); /* current running cores */
 
     /* Calculate location of spin table in BPTR */
     spin_table_addr = (uint8_t*)(BOOT_ROM_ADDR +
@@ -1188,27 +1276,28 @@ static void hal_mp_up(uint32_t bootpg)
 
     /* Set the boot page translation reigster */
     set32(LCC_BSTRL, bootpg);
-    set32(LCC_BSTAR, LCC_BSTAR_EN | LCC_BSTAR_LAWTRGT(LAW_TRGT_DDR_1) | LAW_SIZE_4KB);
+    set32(LCC_BSTAR, (LCC_BSTAR_EN |
+                      LCC_BSTAR_LAWTRGT(LAW_TRGT_IFC) |
+                      LAW_SIZE_4KB));
+    (void)get32(LCC_BSTAR); /* read back to sync */
 
-    /* Disable time base on inactive core */
-    set32(RCPM_PCTBENR, (1 << !whoami));
+    /* Enable time base on current core only */
+    set32(RCPM_PCTBENR, (1 << whoami));
 
     /* Release the CPU core(s) */
-    up = ((1 << CPU_NUMCORES) - 1);
-    set32(DCFG_BRR, up);
+    set32(DCFG_BRR, all_cores);
     asm volatile("sync; isync; msync");
 
     /* wait for other core to start */
-    cpu_up_mask = (1 << whoami);
     while (timeout) {
         for (i = 0; i < CPU_NUMCORES; i++) {
             uint32_t* entry = (uint32_t*)(spin_table_addr +
                 (i * ENTRY_SIZE) + ENTRY_ADDR_LOWER);
             if (*entry) {
-                cpu_up_mask |= (1 << i);
+                active_cores |= (1 << i);
             }
         }
-        if ((cpu_up_mask & up) == up) {
+        if ((active_cores & all_cores) == all_cores) {
             break;
         }
 
@@ -1220,15 +1309,15 @@ static void hal_mp_up(uint32_t bootpg)
         wolfBoot_printf("MP: Timeout enabling additional cores!\n");
     }
 
-    /* Disable our timebase */
-    set32(RCPM_PCTBENR, (1 << whoami));
+    /* Disable all timebases */
+    set32(RCPM_PCTBENR, 0);
 
     /* Reset our timebase */
     mtspr(SPRN_TBWU, 0);
     mtspr(SPRN_TBWL, 0);
 
     /* Enable timebase for all cores */
-    set32(RCPM_PCTBENR, (1 << 0) | (1 << 1));
+    set32(RCPM_PCTBENR, all_cores);
 }
 
 static void hal_mp_init(void)
@@ -1249,7 +1338,7 @@ static void hal_mp_init(void)
     /* map reset page to bootpg so we can copy code there */
     disable_tlb1(i_tlb);
     set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, /* tlb, epn, rpn */
-        MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, /* perms, wimge */
+        MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
         0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
     /* copy startup code to virtually mapped boot address */
@@ -1284,6 +1373,11 @@ void hal_init(void)
         wolfBoot_printf("QE: Engine init failed!\n");
     }
 #endif
+#ifdef ENABLE_FMAN
+    if (hal_fman_init() != 0) {
+        wolfBoot_printf("FMAN: init failed!\n");
+    }
+#endif
 #ifdef ENABLE_MP
     hal_mp_init();
 #endif

hal/spi/spi_drv_stm32.h

@@ -333,7 +333,7 @@
 #define SPI1_BASE (0x40013000) /* SPI1 base address */
 #endif
 
-#define SPI1_APB2_CLOCK_ER_VAL 	(1 << 12)
+#define SPI1_APB2_CLOCK_ER_VAL     (1 << 12)
 
 #define SPI1_CR1      (*(volatile uint32_t *)(SPI1_BASE))
 #define SPI1_CR2      (*(volatile uint32_t *)(SPI1_BASE + 0x04))
@@ -342,21 +342,21 @@
 
 #define SPI_CR1_CLOCK_PHASE         (1 << 0)
 #define SPI_CR1_CLOCK_POLARITY      (1 << 1)
-#define SPI_CR1_MASTER	    		(1 << 2)
-#define SPI_CR1_BAUDRATE        	(0x07 << 3)
-#define SPI_CR1_SPI_EN		    	(1 << 6)
-#define SPI_CR1_LSBFIRST		    (1 << 7)
-#define SPI_CR1_SSI			        (1 << 8)
-#define SPI_CR1_SSM			        (1 << 9)
+#define SPI_CR1_MASTER              (1 << 2)
+#define SPI_CR1_BAUDRATE            (0x07 << 3)
+#define SPI_CR1_SPI_EN              (1 << 6)
+#define SPI_CR1_LSBFIRST            (1 << 7)
+#define SPI_CR1_SSI                 (1 << 8)
+#define SPI_CR1_SSM                 (1 << 9)
 #define SPI_CR1_16BIT_FORMAT        (1 << 11)
-#define SPI_CR1_TX_CRC_NEXT			(1 << 12)
-#define SPI_CR1_HW_CRC_EN			(1 << 13)
-#define SPI_CR1_BIDIOE			    (1 << 14)
-#define SPI_CR2_SSOE			    (1 << 2)
-
-#define SPI_SR_RX_NOTEMPTY  	    (1 << 0)
-#define SPI_SR_TX_EMPTY			    (1 << 1)
-#define SPI_SR_BUSY			        (1 << 7)
+#define SPI_CR1_TX_CRC_NEXT         (1 << 12)
+#define SPI_CR1_HW_CRC_EN           (1 << 13)
+#define SPI_CR1_BIDIOE              (1 << 14)
+#define SPI_CR2_SSOE                (1 << 2)
+
+#define SPI_SR_RX_NOTEMPTY          (1 << 0)
+#define SPI_SR_TX_EMPTY             (1 << 1)
+#define SPI_SR_BUSY                 (1 << 7)
 
 
 /* GPIO */

include/image.h

@@ -668,7 +668,7 @@ static inline int wb_flash_write_verify_word(struct wolfBoot_image *img,
 #define UBOOT_IMG_HDR_SZ    64
 
 /* --- Flattened Device Tree Blob */
-#define UBOOT_FDT_MAGIC	    0xEDFE0DD0UL
+#define UBOOT_FDT_MAGIC     0xEDFE0DD0UL
 
 #ifndef EXT_ENCRYPTED
 #define WOLFBOOT_MAX_SPACE (WOLFBOOT_PARTITION_SIZE - \

src/boot_ppc_mp.S

@@ -30,7 +30,7 @@
 #ifndef INTVEC_ADDR
 /* workaround to use isr_empty for all interrupts, for real IRQ's adjust the
  * offset and define additional interrupts at those offsets */
-#define INTVEC_ADDR(n) (BOOT_ROM_SIZE + (n * 0x0))
+#define INTVEC_ADDR(n) isr_empty@l
 #endif
 
 /* Additional cores (mp) assembly code for core minimum startup and spin table.