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NXP P1021/T1024 fixes and cleanups for multi-core. Fixes "cpu-release…
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…-addr" to use 64-bit value. Adds secondary cached boot page. Adds L2 cache to multi-core.
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@dgarske
dgarske committed Jan 3, 2024
1 parent 654ade8 commit 3693903
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Showing 7 changed files with 309 additions and 230 deletions.
60 changes: 33 additions & 27 deletions hal/nxp_p1021.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,22 +22,24 @@
#include "target.h"
#include "image.h"
#include "printf.h"
#include <string.h>
#include "string.h"

#include "nxp_ppc.h"

/* Debugging */
/* #define DEBUG_EXT_FLASH */
/* #define DEBUG_ESPI 1 */

/* Tests */
/* #define TEST_DDR */
/* #define TEST_FLASH */
/* #define TEST_TPM */

#define ENABLE_ELBC /* Flash Controller */
#define ENABLE_BUS_CLK_CALC

#ifndef BUILD_LOADER_STAGE1
/* Tests */
#if 0
#define TEST_DDR
#define TEST_FLASH
#define TEST_TPM
#endif
#define ENABLE_PCIE
#define ENABLE_CPLD /* Board Configuration and Status Registers (BCSR) */
#define ENABLE_CONF_IO
Expand All @@ -50,6 +52,7 @@
/* #define ENABLE_QE_CRC32 */ /* CRC32 check on QE disabled by default */
#endif

/* Foward declarations */
#if defined(ENABLE_DDR) && defined(TEST_DDR)
static int test_ddr(void);
#endif
Expand Down Expand Up @@ -421,8 +424,8 @@ enum elbc_amask_sizes {
#define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */

#define DDR_SDRAM_CFG_MEM_EN 0x80000000 /* SDRAM interface logic is enabled */
#define DDR_SDRAM_CFG_32_BE 0x00080000
#define DDR_SDRAM_CFG_ECC_EN 0x20000000
#define DDR_SDRAM_CFG_32_BE 0x00080000
#define DDR_SDRAM_CFG_2_D_INIT 0x00000010 /* data initialization in progress */
#define DDR_SDRAM_CFG_BI 0x00000001 /* Bypass initialization */

Expand Down Expand Up @@ -894,7 +897,7 @@ static void hal_ddr_init(void)
/* Map LAW for DDR */
set_law(6, 0, DDR_ADDRESS, LAW_TRGT_DDR, LAW_SIZE_512MB, 0);

/* If DDR is not already enabled */
/* If DDR is already enabled then just return */
if ((get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN)) {
return;
}
Expand Down Expand Up @@ -1379,7 +1382,7 @@ static int hal_qe_init(void)
set32(QE_SDMA_SDAQMR, 0);

/* Allocate 2KB temporary buffer for sdma */
sdma_base = 0;
sdma_base = 0; /* offset in QE_MURAM */
set32(QE_SDMA_SDEBCR, sdma_base & QE_SDEBCR_BA_MASK);

/* Clear sdma status */
Expand All @@ -1401,28 +1404,25 @@ static int hal_qe_init(void)
#ifdef ENABLE_MP

/* from boot_ppc_core.S */
extern uint32_t _mp_page_start;
extern uint32_t _secondary_start_page;
extern uint32_t _second_half_boot_page;
extern uint32_t _spin_table;
extern uint32_t _spin_table_addr;
extern uint32_t _bootpg_addr;

/* Startup additional cores with spin table and synchronize the timebase */
static void hal_mp_up(uint32_t bootpg)
{
uint32_t up, cpu_up_mask, whoami, bpcr, devdisr;
uint8_t *spin_table_addr;
int timeout = 50, i;

/* Get current running core number */
whoami = get32(PIC_WHOAMI);

/* Calculate location of spin table in BPTR */
spin_table_addr = (uint8_t*)(BOOT_ROM_ADDR +
((uint32_t)&_spin_table - (uint32_t)&_mp_page_start));

wolfBoot_printf("MP: Starting core 2 (spin table %p)\n",
spin_table_addr);
wolfBoot_printf("MP: Starting core 2 (boot page %p, spin table %p)\n",
bootpg, (uint32_t)&_spin_table);

/* Set the boot page translation reigster */
/* Set the boot page translation register */
set32(RESET_BPTR, RESET_BPTR_EN | RESET_BPTR_BOOTPG(bootpg));

/* Disable time base on inactive core */
Expand All @@ -1444,8 +1444,8 @@ static void hal_mp_up(uint32_t bootpg)
cpu_up_mask = (1 << whoami);
while (timeout) {
for (i = 0; i < CPU_NUMCORES; i++) {
uint32_t* entry = (uint32_t*)(spin_table_addr +
(i * ENTRY_SIZE) + ENTRY_ADDR_LOWER);
uint32_t* entry = (uint32_t*)(
(uint8_t*)&_spin_table + (i * ENTRY_SIZE) + ENTRY_ADDR_LOWER);
if (*entry) {
cpu_up_mask |= (1 << i);
}
Expand Down Expand Up @@ -1480,23 +1480,29 @@ static void hal_mp_up(uint32_t bootpg)

static void hal_mp_init(void)
{
uint32_t *fixup = (uint32_t*)&_mp_page_start;
uint32_t *fixup = (uint32_t*)&_secondary_start_page;
uint32_t bootpg;
int i_tlb = 0; /* always 0 */
size_t i;
const uint32_t *s;
uint32_t *d;
const volatile uint32_t *s;
volatile uint32_t *d;

/* Assign virtual boot page at end of DDR */
bootpg = DDR_ADDRESS + DDR_SIZE - BOOT_ROM_SIZE;

/* Store the boot page address for use by additional CPU cores */
_bootpg_addr = bootpg;
_bootpg_addr = (uint32_t)&_second_half_boot_page;

/* Store location of spin table for other cores */
_spin_table_addr = (uint32_t)&_spin_table;

/* Flush bootpg before copying to invalidate any stale cache lines */
flush_cache(bootpg, BOOT_ROM_SIZE);

/* map reset page to bootpg so we can copy code there */
/* Map reset page to bootpg so we can copy code there */
disable_tlb1(i_tlb);
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, /* perms, wimge */
set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn, urpn */
(MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), /* perms, wimge */
0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */

/* copy startup code to virtually mapped boot address */
Expand Down
27 changes: 24 additions & 3 deletions hal/nxp_ppc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -433,11 +433,32 @@

/* L2 Cache */
#if defined(CORE_E6500)
/* L2 Cache Control - E6500CORERM 2.2.3 Memory-mapped registers (MMRs) */
#define L2_CLUSTER_BASE(n) (CCSRBAR + 0xC20000 + (n * 0x40000))
#define L2PID(n) (0x200 + (n * 0x10)) /* L2 Cache Partitioning ID */
#define L2PIR(n) (0x208 + (n * 0x10)) /* L2 Cache Partitioning Allocation */
#define L2PWR(n) (0x20C + (n * 0x10)) /* L2 Cache Partitioning Way */

/* MMRs */
#define L2CSR0 0x000 /* L2 Cache Control and Status 0 */
#define L2CSR1 0x004 /* L2 Cache Control and Status 1 */
#define L2CFG0 0x008 /* L2 Cache Configuration */
#else
#ifdef CORE_E5500
/* L2 Cache Control - E5500RM 2.15 L2 Cache Registers */
#define L2_BASE (CCSRBAR + 0x20000)
#else
/* E500 */
#define L2_BASE (CCSRBAR + 0x20000)
#define L2CTL 0x000 /* 0xFFE20000 - L2 control register */
#define L2SRBAR0 0x100 /* 0xFFE20100 - L2 SRAM base address register */

#define L2CTL_EN (1 << 31) /* L2 enable */
#define L2CTL_INV (1 << 30) /* L2 invalidate */
#define L2CTL_SIZ(n) (((n) & 0x3) << 28) /* 2=256KB (always) */
#define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */
#endif

/* SPR */
#define L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
#define L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
Expand All @@ -450,8 +471,6 @@
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */

#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
Expand Down Expand Up @@ -715,6 +734,7 @@ extern void dcache_disable(void);
/* For multiple core spin table communication */
/* The spin table must be WING 0b001x (memory-coherence required) */
/* For older PPC compat use dcbf to flush spin table entry */
/* Note: spin-table must be cache-line aligned in memory */
#define EPAPR_MAGIC (0x45504150) /* Book III-E CPUs */
#define ENTRY_ADDR_UPPER 0
#define ENTRY_ADDR_LOWER 4
Expand All @@ -727,6 +747,7 @@ extern void dcache_disable(void);
#define ENTRY_R6_UPPER 24
#define ENTRY_R6_LOWER 28

#define ENTRY_SIZE CACHE_LINE_SIZE /* note: spin-table shall be cache-line size aligned in memory */

#define ENTRY_SIZE 64

#endif /* !_NXP_PPC_H_ */
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