Added NXP IFC NOR Flash erase/write.

wolfSSL · Oct 4, 2023 · 21d8541 · 21d8541
1 parent 63c5688
commit 21d8541
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Showing 8 changed files with 220 additions and 88 deletions.
diff --git a/config/examples/nxp-t1024.config b/config/examples/nxp-t1024.config
@@ -29,8 +29,8 @@ DEBUG_ELF=0
 # NOR Base Address
 ARCH_FLASH_OFFSET?=0xEC000000
 
-# Flash Sector Size
-WOLFBOOT_SECTOR_SIZE=0x10000
+# Flash Sector Size (128KB)
+WOLFBOOT_SECTOR_SIZE=0x20000
 
 # wolfBoot start address
 WOLFBOOT_ORIGIN=0xEFF40000

diff --git a/docs/Targets.md b/docs/Targets.md
@@ -1265,7 +1265,7 @@ Reset Configuration Word (RCW):
 
 Flash is NOR on IFC CS0 (0x0_EC00_0000) 64MB (default).
 
-Default NOR Flash Memory Layout (64MB):
+Default NOR Flash Memory Layout (64MB) (128KB block, 1K page)
 
 | Description       | Address    | Size                |
 | ----------------- | ---------- | ------------------- |

diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c
@@ -935,15 +935,15 @@ static void hal_ddr_init(void)
 
     /* Set values, but do not enable the DDR yet */
     set32(DDR_SDRAM_CFG, ((DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN)));
-    asm volatile("sync;isync");
+    __asm__ __volatile__("sync;isync");
 
     /* busy wait for ~500us */
     udelay(500);
 
     /* Enable controller */
     reg = get32(DDR_SDRAM_CFG) & ~DDR_SDRAM_CFG_BI;
     set32(DDR_SDRAM_CFG, reg | DDR_SDRAM_CFG_MEM_EN);
-    asm volatile("sync;isync");
+    __asm__ __volatile__("sync;isync");
 
     /* Wait for data initialization to complete */
     while (get32(DDR_SDRAM_CFG_2) & DDR_SDRAM_CFG_2_D_INIT) {
@@ -1438,7 +1438,7 @@ static void hal_mp_up(uint32_t bootpg)
     bpcr = get32(ECM_EEBPCR);
     bpcr |= ECM_EEBPCR_CPU_EN(up);
     set32(ECM_EEBPCR, bpcr);
-    asm volatile("sync; isync; msync");
+    __asm__ __volatile__("sync; isync; msync");
 
     /* wait for other core to start */
     cpu_up_mask = (1 << whoami);

diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h
@@ -545,13 +545,13 @@
 #define WC_STRINGIFY(str) _WC_STRINGIFY_L2(str)
 #endif
 
-#define mtspr(rn, v) asm volatile("mtspr " WC_STRINGIFY(rn) ",%0" : : "r" (v))
+#define mtspr(rn, v) __asm__ __volatile__("mtspr " WC_STRINGIFY(rn) ",%0" : : "r" (v))
 
 #define mfmsr() ({ \
     unsigned int rval; \
-    asm volatile("mfmsr %0" : "=r" (rval)); rval; \
+    __asm__ __volatile__("mfmsr %0" : "=r" (rval)); rval; \
 })
-#define mtmsr(v)     asm volatile("mtmsr %0" : : "r" (v))
+#define mtmsr(v)     __asm__ __volatile__("mtmsr %0" : : "r" (v))
 
 
 #ifndef __ASSEMBLER__