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Progress on NXP T1024 QUICC UCC HDLC issues for booting Integrity OS.
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@dgarske
dgarske committed Dec 21, 2023
1 parent 3684c28 commit 1133ef0
Showing 1 changed file with 74 additions and 15 deletions.
89 changes: 74 additions & 15 deletions hal/nxp_t1024.c
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,9 @@ static void hal_flash_unlock_sector(uint32_t sector);
#define LCC_BSTAR_LAWSZ(n) ((n) & 0x3F)

/* DCFG (Device Configuration/Pin Control) T1024RM 7.3 */
#define DCSRBAR_BASE_HIGH 0xF
#define DCSRBAR_BASE 0xF0000000

#define DCFG_BASE (CCSRBAR + 0xE0000)
#define DCFG_PVR ((volatile uint32_t*)(DCFG_BASE + 0xA0UL))
#define DCFG_SVR ((volatile uint32_t*)(DCFG_BASE + 0xA4UL))
Expand All @@ -115,8 +118,28 @@ static void hal_flash_unlock_sector(uint32_t sector);
/* PCI Express LIODN base register */
#define PCI_BASE(n) (0x240000 + ((n) * 0x10000))
#define PCIE_LIODN(n) ((volatile uint32_t*)(PCI_BASE(n) + 0x40)) /* PEXx_PEX_LBR */
#define BMAN_LIODNR ((volatile uint32_t*)(BMAN_CCSR_BASE + 0xD08))
#define QMAN_LIODNR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xD08))

/* Buffer Manager */
#define BMAN_LIODNR ((volatile uint32_t*)(BMAN_CCSR_BASE + 0xD08))
#define BCSP_ISDR(n) ((volatile uint32_t*)(BMAN_BASE_PHYS + 0x1000E08 + ((n) * 0x1000)))

/* Frame Queue Descriptor (FQD) */
#define FQD_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC04))
#define FQD_AR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC10))
/* Packed Frame Desc riptor Record (PFDR) */
#define PFDR_BARE ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC20))
#define PFDR_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC24))
#define PFDR_AR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC30))

/* QMan */
#define QCSP_BARE ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC80)) /* Base Address (upper) */
#define QCSP_BAR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xC84)) /* Base Address */
/* QMan Software Portals */
#define QMAN_LIODNR ((volatile uint32_t*)(QMAN_CCSR_BASE + 0xD08))
#define QCSP_LIO_CFG(n) ((volatile uint32_t*)(QMAN_CCSR_BASE + 0x1000 + ((n) * 0x10)))
#define QCSP_IO_CFG(n) ((volatile uint32_t*)(QMAN_CCSR_BASE + 0x1004 + ((n) * 0x10)))

#define QCSP_ISDR(n) ((volatile uint32_t*)(QMAN_BASE_PHYS + 0x1000E08 + ((n) * 0x1000)))

/* SCGG (Supplemental Configuration Unit) T1024RM 6.1 */
#define SCFG_BASE (CCSRBAR + 0xFC000)
Expand Down Expand Up @@ -157,10 +180,15 @@ static void hal_flash_unlock_sector(uint32_t sector);
#define QE_CEPICR ((volatile uint32_t*)(QE_BASE + 0x014UL))

#define QE_ENGINE_BASE (CCSRBAR + 0x80000)
#define QE_IRAM (QE_ENGINE_BASE + 0x000UL) /* Instruction RAM registers */
#define QE_IRAM_IADD ((volatile uint32_t*)(QE_IRAM + 0x000UL))
#define QE_IRAM_IDATA ((volatile uint32_t*)(QE_IRAM + 0x004UL))
#define QE_IRAM_IREADY ((volatile uint32_t*)(QE_IRAM + 0x00CUL))
#define QE_IRAM_IADD ((volatile uint32_t*)(QE_ENGINE_BASE + 0x000UL))
#define QE_IRAM_IDATA ((volatile uint32_t*)(QE_ENGINE_BASE + 0x004UL))
#define QE_IRAM_IREADY ((volatile uint32_t*)(QE_ENGINE_BASE + 0x00CUL))

/* T1024 -> Two UCCs — UCC1, UCC3 supported - CMX UCC1/3 Clock Route Register */
#define QE_CMXUCR1 ((volatile uint32_t*)(QE_ENGINE_BASE + 0xC0000 + 0x410UL))

/* Baud-Rate Generator Configuration Registers */
#define BRG_BRGC(n) ((volatile uint32_t*)(QE_ENGINE_BASE + 0xC0000 + 0x640UL + ((n-1) * 0x4)))

#define QE_CP (QE_ENGINE_BASE + 0x100UL) /* Configuration register */
#define QE_CP_CECR ((volatile uint32_t*)(QE_CP + 0x00)) /* command register */
Expand Down Expand Up @@ -205,16 +233,17 @@ static void hal_flash_unlock_sector(uint32_t sector);
*/
#define QMAN_CCSR_BASE (CCSRBAR + 0x318000)
#define QMAN_BASE_PHYS_HIGH 0xF
#define QMAN_BASE_PHYS 0xF6000000

#define QMAN_BASE_PHYS 0xF6000000
#define QMAN_NUM_PORTALS 10

/* T1024RM 10.5.2: Buffer Manager (BMan):
* - BMan block base address: 31_A000h
* - 64 buffer pools
*/
#define BMAN_CCSR_BASE (CCSRBAR + 0x31A000)
#define BMAN_BASE_PHYS_HIGH 0xF
#define BMAN_BASE_PHYS 0xF4000000
#define BMAN_BASE_PHYS 0xF4000000
#define BMAN_NUM_POOLS 64

/* T1024RM 10.5.4: Security and Encryption Engine (SEC)
* - SEC block base address: 30_0000h
Expand Down Expand Up @@ -720,8 +749,6 @@ static void law_init(void)
(MAS3_SX | MAS3_SW | MAS3_SR), (MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_16M, 1);

/* DCSR - 4MB */
#define DCSRBAR_BASE_HIGH 0xF
#define DCSRBAR_BASE 0xF0000000
set_law(5, DCSRBAR_BASE_HIGH, DCSRBAR_BASE, LAW_TRGT_DCSR, LAW_SIZE_4MB, 1);
set_tlb(1, 9, DCSRBAR_BASE,
DCSRBAR_BASE, DCSRBAR_BASE_HIGH,
Expand Down Expand Up @@ -1360,7 +1387,6 @@ void hal_liodn_init(void)
/* ---- QUICC Engine Driver ---- */
#ifdef ENABLE_QE

#define CONFIG_SYS_QMAN_NUM_PORTALS 10
struct qportal_info {
uint16_t dliodn; /* DQRR LIODN */
uint16_t fliodn; /* frame data LIODN */
Expand All @@ -1371,7 +1397,7 @@ struct qportal_info {
#define SET_QP_INFO(dqrr, fdata, off, dest) \
{ .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }

static const struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
static const struct qportal_info qp_info[QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),
Expand Down Expand Up @@ -1458,7 +1484,7 @@ static void qe_issue_cmd(uint32_t cmd, uint32_t sbc, uint8_t mcn,

static int hal_qe_init(void)
{
int ret;
int ret, i;
uint32_t sdma_base;
const struct qe_firmware* fw = (const struct qe_firmware*)QE_FW_ADDR;

Expand Down Expand Up @@ -1493,6 +1519,39 @@ static int hal_qe_init(void)
qe_issue_cmd(QE_RESET, 0, 0, 0);
}

/* Configure QMan software portal base address (QCSP) */
set32(QCSP_BARE, QMAN_BASE_PHYS_HIGH);
set32(QCSP_BAR, QMAN_BASE_PHYS);

/* Configure Frame Queue Descriptor (FQD) */
set32(FQD_BAR, 0);
set32(FQD_AR, 0);

/* Packed Frame Descriptor Record (PFDR) */
set32(PFDR_BARE, 0);
set32(PFDR_BAR, 0);
set32(PFDR_AR, 0);

/* Inhibit BMan/QMan portals by default */
for (i=0; i<QMAN_NUM_PORTALS; i++) {
set32(QCSP_ISDR(i), 0x3FFFFF);
set32(BCSP_ISDR(i), 0x7);
}

/* Setup LIODN */
for (i=0; i<(int)(sizeof(qp_info)/sizeof(struct qportal_info)); i++) {
set32(QCSP_LIO_CFG(i),
(qp_info[i].liodn_offset << 16) | qp_info[i].dliodn);
set32(QCSP_IO_CFG(i),
(qp_info[i].sdest << 16) | qp_info[i].fliodn);
}

/* Setup QUICC Engine UCC 1/3 Clock Route */
set32(QE_CMXUCR1, 0);

/* Set baud rate configuration */
set32(BRG_BRGC(1), 0);

return ret;
}
#endif /* ENABLE_QUICC */
Expand Down Expand Up @@ -1919,7 +1978,7 @@ int hal_dts_fixup(void* dts_addr)
(core * ENTRY_SIZE) + ENTRY_ADDR_LOWER);

fdt_fixup_str(fdt, off, "cpu", "status", (core == 0) ? "okay" : "disabled");
fdt_fixup_val(fdt, off, "cpu", "spin-table", (uint32_t)core_spin_table);
fdt_fixup_val(fdt, off, "cpu", "cpu-release-addr", (uint32_t)core_spin_table);
fdt_fixup_str(fdt, off, "cpu", "enable-method", "spin-table");
fdt_fixup_val(fdt, off, "cpu", "timebase-frequency", TIMEBASE_HZ);
fdt_fixup_val(fdt, off, "cpu", "clock-frequency", hal_get_plat_clk());
Expand Down

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