[RFC] Initial multiclock support in token channels & synthesizable unit tests

src/main/cc/Makefile

@@ -50,99 +50,61 @@ $(OUT_DIR)/$(DESIGN).chain:
 	$(if $(wildcard $(GEN_DIR)/$(DESIGN).chain),cp $(GEN_DIR)/$(DESIGN).chain $@,)
 
 override CXXFLAGS += -I$(midas_dir) -I$(util_dir)
-override LDFLAGS := $(LDFLAGS) -L$(GEN_DIR) -lstdc++ -lpthread -lgmp 
+# The trailing whitespace is important for some reason...
+override LDFLAGS := $(LDFLAGS) -L$(GEN_DIR) -lstdc++ -lpthread -lgmp -lmidas 
 
-design_v = $(GEN_DIR)/$(shim).v
+design_v  := $(GEN_DIR)/$(shim).v
+design_h  := $(GEN_DIR)/$(DESIGN)-const.h
+design_vh := $(GEN_DIR)/$(DESIGN)-const.vh
 driver_h = $(foreach t, $(DRIVER), $(wildcard $(dir $(t))/*.h))
 endpoint_h := $(wildcard $(endpoint_dir)/*.h)
 endpoint_cc := $(wildcard $(endpoint_dir)/*.cc)
 endpoint_o := $(patsubst $(endpoint_dir)/%.cc, $(GEN_DIR)/%.o, $(endpoint_cc))
-$(endpoint_o): $(GEN_DIR)/%.o: $(endpoint_dir)/%.cc $(GEN_DIR)/$(DESIGN)-const.h $(endpoint_h)
+$(endpoint_o): $(GEN_DIR)/%.o: $(endpoint_dir)/%.cc $(design_h) $(endpoint_h)
 	$(CXX) $(CXXFLAGS) -c -o $@ $< -include $(word 2, $^)
 
 platform_files := simif simif_$(PLATFORM) sample/sample
 platform_h := $(addprefix $(midas_dir)/, $(addsuffix .h, $(platform_files)))
 platform_cc := $(addprefix $(midas_dir)/, $(addsuffix .cc, $(platform_files) sample/simif_sample))
 platform_o := $(addprefix $(GEN_DIR)/, $(addsuffix .o, $(platform_files) sample/simif_sample))
 
-$(platform_o): $(GEN_DIR)/%.o: $(midas_dir)/%.cc $(GEN_DIR)/$(DESIGN)-const.h $(platform_h)
+$(platform_o): $(GEN_DIR)/%.o: $(midas_dir)/%.cc $(design_h) $(platform_h)
 	mkdir -p $(dir $@)
 	$(CXX) $(CXXFLAGS) -c -o $@ $< -include $(word 2, $^)
 
-$(OUT_DIR)/$(DESIGN)-$(PLATFORM): $(GEN_DIR)/$(DESIGN)-const.h $(lib) $(DRIVER) $(driver_h) $(platform_o) $(endpoint_o)
+$(OUT_DIR)/$(DESIGN)-$(PLATFORM): $(design_h) $(lib) $(DRIVER) $(driver_h) $(platform_o) $(endpoint_o)
 	mkdir -p $(OUT_DIR)
 	$(CXX) $(CXXFLAGS) -include $< \
 	-o $@ $(DRIVER) $(dramsim_o) $(lib_o) $(platform_o) $(endpoint_o) $(LDFLAGS)
 
 $(PLATFORM): $(OUT_DIR)/$(DESIGN)-$(PLATFORM) $(OUT_DIR)/$(DESIGN).chain
 
-emul_files := simif simif_emul emul/mmio_$(PLATFORM) sample/sample
-emul_h := $(addprefix $(midas_dir)/, $(addsuffix .h, $(emul_files) emul/mmio))
-emul_cc := $(addprefix $(midas_dir)/, $(addsuffix .cc, $(emul_files) sample/simif_sample))
-emul_v := $(v_dir)/emul_$(PLATFORM).v
+# Sources for building MIDAS-level simulators. Must be defined before sources VCS/Verilator Makefrags
+override CFLAGS += -include $(design_h)
 
-# Compile verilator emulation binary
-VERILATOR ?= verilator --cc --exe
-override VERILATOR_FLAGS := --assert -Wno-STMTDLY -O3 \
-	-CFLAGS "$(CXXFLAGS)" -LDFLAGS "$(LDFLAGS) -lmidas" \
-	$(VERILATOR_FLAGS)
+emul_files := simif simif_emul emul/mmio_$(PLATFORM) sample/sample
+emul_h     := $(driver_h) $(endpoint_h)  $( $(addprefix $(midas_dir)/, $(addsuffix .h, $(emul_files) emul/mmio)))
+# This includes c sources and static libraries
+emul_cc    := $(DRIVER) $(endpoint_cc) $(addprefix $(midas_dir)/, $(addsuffix .cc, $(emul_files) sample/simif_sample)) $(lib)
+emul_v     := $(design_vh) $(design_v)
 
+# The lop level module must be called out for verilator
 ifeq ($(PLATFORM),zynq)
 top_module = ZynqShim
 endif
 ifeq ($(PLATFORM),f1)
 top_module = F1Shim
 endif
-
-$(OUT_DIR)/V$(DESIGN): $(GEN_DIR)/$(DESIGN)-const.h $(design_v) $(lib) $(DRIVER) $(driver_h) $(emul_cc) $(emul_h) $(endpoint_cc) $(endpoint_h)
-	mkdir -p $(OUT_DIR)
-	rm -rf $(GEN_DIR)/V$(DESIGN).csrc
-	$(VERILATOR) $(VERILATOR_FLAGS) --top-module $(top_module) -Mdir $(GEN_DIR)/V$(DESIGN).csrc \
-	-CFLAGS "-include $< -include $(GEN_DIR)/V$(DESIGN).csrc/V$(top_module).h" \
-	-o $@ $(design_v) $(DRIVER) $(emul_cc) $(endpoint_cc)
-	$(MAKE) -C $(GEN_DIR)/V$(DESIGN).csrc -f V$(top_module).mk
-
-$(OUT_DIR)/V$(DESIGN)-debug: $(GEN_DIR)/$(DESIGN)-const.h $(design_v) $(lib) $(DRIVER) $(driver_h) $(emul_cc) $(emul_h) $(endpoint_cc) $(endpoint_h)
-	mkdir -p $(OUT_DIR)
-	rm -rf $(GEN_DIR)/V$(DESIGN)-debug.csrc
-	$(VERILATOR) $(VERILATOR_FLAGS) --trace --top-module $(top_module) -Mdir $(GEN_DIR)/V$(DESIGN)-debug.csrc \
-	-CFLAGS "-include $< -include $(GEN_DIR)/V$(DESIGN)-debug.csrc/V$(top_module).h" \
-	-o $@ $(design_v) $(DRIVER) $(emul_cc) $(endpoint_cc)
-	$(MAKE) -C $(GEN_DIR)/V$(DESIGN)-debug.csrc -f V$(top_module).mk
+include rtlsim/Makefrag-verilator
 
 verilator: $(OUT_DIR)/V$(DESIGN) $(OUT_DIR)/$(DESIGN).chain $(OUT_DIR)/dramsim2_ini
 verilator-debug: $(OUT_DIR)/V$(DESIGN)-debug $(OUT_DIR)/$(DESIGN).chain $(OUT_DIR)/dramsim2_ini
 
-# Compile VCS emulation binary
-VCS ?= vcs -full64
-override VCS_FLAGS := -quiet -timescale=1ns/1ps +v2k +rad +vcs+initreg+random +vcs+lic+wait \
-	 -notice -line +lint=all,noVCDE,noONGS,noUI -quiet -debug_pp +no_notifier -e vcs_main -cpp $(CXX) \
-	-CFLAGS "$(CXXFLAGS) -DVCS -I$(VCS_HOME)/include" \
-	-LDFLAGS "$(LDFLAGS) -lmidas" \
-	+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
-	+define+RANDOMIZE_MEM_INIT \
-	+define+RANDOMIZE_REG_INIT \
-	+define+RANDOMIZE_GARBAGE_ASSIGN \
-	+define+RANDOMIZE_INVALID_ASSIGN \
-	$(VCS_FLAGS)
-
-$(OUT_DIR)/$(DESIGN): $(GEN_DIR)/$(DESIGN)-const.h $(design_v) $(emul_v) $(lib) $(DRIVER) $(driver_h) $(emul_cc) $(emul_h) $(endpoint_cc) $(endpoint_h)
-	mkdir -p $(OUT_DIR)
-	rm -rf $(GEN_DIR)/$(DESIGN).csrc
-	rm -rf $(OUT_DIR)/$(DESIGN).daidir
-	$(VCS) $(VCS_FLAGS) -Mdir=$(GEN_DIR)/$(DESIGN).csrc +vc+list \
-	+define+STOP_COND=!emul.reset +define+PRINTF_COND=!emul.reset \
-	-CFLAGS "-include $<" \
-	-o $@ $(GEN_DIR)/$(DESIGN)-const.vh $(design_v) $(emul_v) $(lib) $(DRIVER) $(emul_cc) $(endpoint_cc)
-
-$(OUT_DIR)/$(DESIGN)-debug: $(GEN_DIR)/$(DESIGN)-const.h $(design_v) $(emul_v) $(lib) $(DRIVER) $(driver_h) $(emul_cc) $(emul_h) $(endpoint_cc) $(endpoint_h)
-	mkdir -p $(OUT_DIR)
-	rm -rf $(GEN_DIR)/$(DESIGN)-debug.csrc
-	rm -rf $(OUT_DIR)/$(DESIGN)-debug.daidir
-	$(VCS) $(VCS_FLAGS) -Mdir=$(GEN_DIR)/$(DESIGN)-debug.csrc +vc+list \
-	+define+STOP_COND=!emul.reset +define+PRINTF_COND=!emul.reset +define+DEBUG \
-	-CFLAGS "-include $<" \
-	-o $@ $(GEN_DIR)/$(DESIGN)-const.vh $(design_v) $(emul_v) $(lib) $(DRIVER) $(emul_cc) $(endpoint_cc)
+# Add an extra wrapper source for VCS simulators
+vcs_wrapper_v := $(v_dir)/emul_$(PLATFORM).v
+TB := emul
+VCS_FLAGS := -e vcs_main
+include rtlsim/Makefrag-vcs
 
 vcs: $(OUT_DIR)/$(DESIGN) $(OUT_DIR)/$(DESIGN).chain $(OUT_DIR)/dramsim2_ini
 vcs-debug: $(OUT_DIR)/$(DESIGN)-debug $(OUT_DIR)/$(DESIGN).chain $(OUT_DIR)/dramsim2_ini

src/main/cc/rtlsim/Makefrag-vcs

@@ -0,0 +1,43 @@
+# VCS RTL Simulation Makefrag
+#
+# This makefrag stores common recipes for building RTL simulators with VCS
+#
+# Compulsory variables:
+#  All those described Makefrag-verilator
+#  vcs_wrapper_v: An additional verilog wrapper around the DUT not used in verilator
+#  CLOCK_PERIOD: Self explanatory
+#  TB := The top level module on which the stop and printf conditions are defined 
+#
+
+VCS ?= vcs -full64
+override VCS_FLAGS := -quiet -timescale=1ns/1ps +v2k +rad +vcs+initreg+random +vcs+lic+wait \
+	-notice -line +lint=all,noVCDE,noONGS,noUI -quiet -debug_pp +no_notifier -cpp $(CXX) \
+ 	-Mdir=$(GEN_DIR)/$(DESIGN)-debug.csrc \
+	+vc+list \
+	-CFLAGS "$(CXXFLAGS) $(CFLAGS) -DVCS -I$(VCS_HOME)/include" \
+	-LDFLAGS "$(LDFLAGS)" \
+	-sverilog \
+	+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
+	+define+RANDOMIZE_MEM_INIT \
+	+define+RANDOMIZE_REG_INIT \
+	+define+RANDOMIZE_GARBAGE_ASSIGN \
+	+define+RANDOMIZE_INVALID_ASSIGN \
+	+define+STOP_COND=!$(TB).reset \
+	+define+PRINTF_COND=!$(TB).reset \
+	$(VCS_FLAGS)
+
+vcs_v := $(emul_v) $(vcs_wrapper_v)
+
+$(OUT_DIR)/$(DESIGN): $(vcs_v) $(emul_cc) $(emul_h)
+	mkdir -p $(OUT_DIR)
+	rm -rf $(GEN_DIR)/$(DESIGN).csrc
+	rm -rf $(OUT_DIR)/$(DESIGN).daidir
+	$(VCS) $(VCS_FLAGS) \
+	-o $@ $(vcs_v) $(emul_cc)
+
+$(OUT_DIR)/$(DESIGN)-debug: $(vcs_v) $(emul_cc) $(emul_h)
+	mkdir -p $(OUT_DIR)
+	rm -rf $(GEN_DIR)/$(DESIGN)-debug.csrc
+	rm -rf $(OUT_DIR)/$(DESIGN)-debug.daidir
+	$(VCS) $(VCS_FLAGS) +define+DEBUG \
+	-o $@ $(vcs_v) $(emul_cc)

src/main/cc/rtlsim/Makefrag-verilator

@@ -0,0 +1,36 @@
+# Verilator RTL Simulation Makefrag
+#
+# This makefrag stores common recipes for building RTL simulators with Verilator
+#
+# Compulsory variables:
+# 	OUT_DIR: See Makefile
+# 	GEN_DIR: See Makefile
+# 	DESIGN: See Makefile
+# 	emul_cc: C++ sources
+# 	emul_h: C++ headers
+# 	emul_v: verilog sources and headers
+#
+# Verilator Only:
+#   top_module: The top of the DUT
+
+VERILATOR ?= verilator --cc --exe
+override VERILATOR_FLAGS := --assert -Wno-STMTDLY -O3 \
+	-CFLAGS "$(CXXFLAGS) $(CFLAGS)" \
+	-LDFLAGS "$(LDFLAGS) " \
+	$(VERILATOR_FLAGS)
+
+$(OUT_DIR)/V$(DESIGN): $(emul_v) $(emul_cc) $(emul_h)
+	mkdir -p $(OUT_DIR)
+	rm -rf $(GEN_DIR)/V$(DESIGN).csrc
+	$(VERILATOR) $(VERILATOR_FLAGS) --top-module $(top_module) -Mdir $(GEN_DIR)/V$(DESIGN).csrc \
+	-CFLAGS "-include $(GEN_DIR)/V$(DESIGN).csrc/V$(top_module).h" \
+	-o $@ $(emul_v) $(emul_cc)
+	$(MAKE) -C $(GEN_DIR)/V$(DESIGN).csrc -f V$(top_module).mk
+
+$(OUT_DIR)/V$(DESIGN)-debug: $(emul_v) $(emul_cc) $(emul_h)
+	mkdir -p $(OUT_DIR)
+	rm -rf $(GEN_DIR)/V$(DESIGN)-debug.csrc
+	$(VERILATOR) $(VERILATOR_FLAGS) --trace --top-module $(top_module) -Mdir $(GEN_DIR)/V$(DESIGN)-debug.csrc \
+	-CFLAGS "-include $(GEN_DIR)/V$(DESIGN)-debug.csrc/V$(top_module).h" \
+	-o $@ $(emul_v) $(emul_cc)
+	$(MAKE) -C $(GEN_DIR)/V$(DESIGN)-debug.csrc -f V$(top_module).mk