Do you support uvm_component_param_utils? Any alternative approach? Any example?

[sbhutada]

Is there an example that shows parameterized UVM components and objects? Thanks.

[tpoikela]

Do you have a usecase for this? Python does not need nor does it have parameters like SystemVerilog. You can set any variable during any UVM phase in uvm-python.

[sbhutada]

I will send a dummy test case and see what you might suggest. How well is the sv2py.pl to migrate things over to Python? I am seeing some issues. Thanks

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On Wed, Feb 14, 2024 at 12:26 PM Tuomas Poikela ***@***.***> wrote: Do you have a usecase for this? Python does not need nor does it have parameters like SystemVerilog. You can set any variable during any UVM phase in uvm-python. — Reply to this email directly, view it on GitHub <#51 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AET6VI4TXIZKLAGECZ6GO33YTUMYNAVCNFSM6AAAAABDHAG5BOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSNBUGUZTQMRZG4> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[tpoikela]

sv2py.pl is meant only for initial conversion, but you need to do manual and fixes adjustments usually, depending on how close your SystemVerilog is to the SV UVM library (since I wrote the script mainly for this conversion).

If you want to have support for particular conversions, you can file a specific issue, or fix it yourself a submit a pull request. As far as I know, there is no sv2py conversion script available that would work 100% with any SV files.