Skip to content

Issues: tpoikela/uvm-python

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

9 Open 16 Closed
9 Open 16 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

How to generate file dumpwave by code uvm-python?
#54 opened Aug 26, 2024 by AnhHonag
It seems there are some problems in starting the sequence by using the way of UVMConfigDb.set(self, "xxx.xxx_vsqr.main_phase", "default_sequence", self.vseq ).
#53 opened Aug 22, 2024 by 717-yq
3
Do you support uvm_component_param_utils? Any alternative approach? Any example?
#51 opened Feb 13, 2024 by sbhutada
3
examples/sv is failing ... any ideas?
#50 opened Jan 13, 2024 by sbhutada
1
Is there a way to mix SystemVerilog UVM and UVM-Python environments?
#47 opened Jan 5, 2024 by sbhutada
2
uvm hw reset sequence bug
#41 opened Apr 9, 2023 by SikoVerilog
2
Latest version of cocotb Verilator will always issue error %Error-TIMESCALEMOD.
#37 opened Mar 14, 2021 by jg-fossh
4
Correct way to clean up UVM objects
#36 opened Feb 16, 2021 by sjalloq
2
registers/vertical_reuse blk-level simulation fails with ghdl/VHDL DUT
#26 opened Dec 20, 2020 by tpoikela
11
ProTip! Add no:assignee to see everything that’s not assigned.