Split USB clock domains between physical and endpoint layers #40
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This patch separates the USB physical layer, which runs at 48 MHz, from the end point code, which can run at 12 to 24 MHz. This has been tested on the TinyFPGA BX and the Tomu FOMU (ice40up5k).
It also includes the patches by @smunaut to fix combinatorial loops, which allows
icetime
to compute timing estimates, and updates tobootloader.v
and theMakefile
to usenextpnr-ice40
for place and route on the BX.