WIP: ULX3S support #54
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icecube doesn't care about init values, but yosys does and you can't satisfy them with HW RAM module. So here we remove all the init values and we make sure the reads are not dependent on the reset line Signed-off-by: Sylvain Munaut <[email protected]>
Signed-off-by: Sylvain Munaut <[email protected]>
…atches If you don't assign all 'reg's in a process, this effectively describes a latch, and the HW doesn't have any HW latches which leads yosys to create a logic loop, which is definitely not good in FPGA ! Signed-off-by: Sylvain Munaut <[email protected]>
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@osresearch - FYI There isn't much work going into this bootloader at the moment. Most people have moved over to the ValentyUSB / Foboot stuff that @xobs is working on. |
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Just flashed a brand new board and found a few issues in the documentation. Updated it as well as fixed the return code from security page write. |
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Preliminary support for the ULX3S ECP5 fpga dev board. I wasn't able to make it work with the USB serial device in master, but it works fine with the split clock one in #40
The bootstrap procedure to install the firmware and configure it needs more documentation. Sample JSON files are included.