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build(deps): bump actions/upload-artifact from 3 to 4 #243
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build(deps): bump actions/upload-artifact from 3 to 4 #243
Commits on Jan 10, 2024
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Documentation: add NuttX-12.4.0 release notes
Add release notes for 12.4.0 release Signed-off-by: Alin Jerpelea <[email protected]>
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Commits on Feb 12, 2024
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boards/riscv/mpfs/icicle/configs/standalone: Add a standalone target
- boots from eNVM - uses lim memory for RAM - has console on uart 0 - has procfs enabled - has most of nsh commands enabled Signed-off-by: Jukka Laitinen <[email protected]>
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Fix the check workflow for tiiuae repo
- Change git repository urls to point to our tiiuae repos for nuttx & nuttx apps - Remove most of the the build steps, leave just arm-12 and riscv; arm-12 has a build for stm32f7, and riscv for mpfs Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/opensbi/Make.defs: Switch opensbi to the nuttx/size o…
…ptimized version in tiiuae repo Signed-off-by: Jukka Laitinen <[email protected]>
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[REVERTME] arch/risc-v/src/mpfs/mpfs_ethernet.c: Hack the ethernet dr…
…iver to re-initialize on rx timeout If the interface is UP, and no packets are received in 30s, re-initialize the interface by calling the already implemented mpfs_txtimeout_expiry. This is a temporary workaround for a bug where IF might be UP and working but packets can only be transmitted. Receive side just doesn't work at all. The original bug can be re-produced easily by disconnecting and reconnecting the ethernet cable while the IF is up. Signed-off-by: Jukka Laitinen <[email protected]>
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[HACK] Set SD-card speed to 50MHz
SD-card clock speed is just forced to 50MHz. Note that to be correct, one should first set the SD-card into high-speed mode, but currently NuttX doesn't support this. With our cards, just setting the interface to 50MHz seems to work fine, and it removes the issue with 25MHZ clock causing disturbance on GPS bands. Typically cards which support high-speed mode just work with 50MHz interface clock. This patch should be reverted when the NuttX supports high-speed mode, and we can properly set it. Signed-off-by: Jukka Laitinen <[email protected]>
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Fix standalone defconfig for CI
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_clockconfig.c: Flag out code only used in b…
…ootloader This removes the need to have all the DDR/clock configuration related "LIBERODEFS" flags defined, when not building a standalone/coldboot configuration All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER Signed-off-by: Jukka Laitinen <[email protected]>
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mpfs/emmcsd: [HACK] Set 8-bit data width and DDR HS mode for eMMC
This is not the correct way to do this, but it gives a nice perf. boost
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drivers/net/rpmsgdrv.c: Support only TRANSFER commands
All other commands are disabled in send_recv(). Signed-off-by: Jani Paalijarvi <[email protected]>
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arch/risc-v/src/mpfs/mpfs_fpga_canfd.c: Fix CONFIG_DEBUG_CAN_INFO ifd…
…ef and forward declare devif_loopback Signed-off-by: Jukka Laitinen <[email protected]>
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boards/risc-v/mpfs/icicle/configs/canfd/defconfig: Normalize
Signed-off-by: Jukka Laitinen <[email protected]>
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remove devif_loopback in canfd driver since it is now devif_poll func…
… that takes care of the need for loopback
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Remove MPFS_IHC_LINUX_ON_HART4 from default configurations
Enable LINUX_ON_HART4 in rpmsg-ch2 defconfig of ICICLE board. Remove LINUX_ON_HART4 config from rpmsg-ch1 defconfig of ICICLE board.
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arch/arm/src/stm32f7/stm32_ethernet.c: Fix "unused variable" warning
Fix build warning when CONFIG_STM32F7_AUTONEG is not set Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_userspace.c: Map MTIME into userspace reser…
…ved IO area in protected build Signed-off-by: Jukka Laitinen <[email protected]>
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boards/risc-v/mpfs/icicle: Add USRIO area for userspace IO mappings
Signed-off-by: Jukka Laitinen <[email protected]>
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Add mpfs crypto driver into nuttx build
Signed-off-by: Jukka Laitinen <[email protected]>
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mpfs/mpfs_mm_init: Add the MTIME user mapping for kernel mode as well
Just a temporary patch, need to implement some kind of scalable solution for this. It might be a good idea to map something else for the user to avoid using ecall to enter the kernel for simple reads ? Also, increase the L3 table size
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arch/risc-v/src/mpfs/Kconfig: Don't source crypto/Kconfig
There is no make step executed for this directory before the Kconfigure, so all Kconfig's just need to be in-tree Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/crypto.defs: Update to include mpfs_systemservice.c
Signed-off-by: Jukka Laitinen <[email protected]>
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emmc interrupt blackout issue fix
sendfifo() function need enable BWR_IE before checking if BWE is enabled to avoid BWE to be activated between the BWE check and BWR interrupt enabling, which causes the interrupt to be missed and Data Timeout error.
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mpfs/mpfs_userspace: Increase user space size to 8MB
The user i/o area goes over 4MB, so need more page tables
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risc-v/mpfs: serial: add fpga uarts
Add FPGA serial support, including console capabilities. FPGA has UARTs from 0-7, so all UARTs starting from 5 depend on FPGA. Signed-off-by: Eero Nurkkala <[email protected]>
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Add CONFIG_MPFS_SPI flag to define using SOC hard-ip SPI block
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs: Remove CONFIG_MPFS_COREPWMx_PWMCLK configs
These are always the same as FPGA peripheral clock, so use that directly Signed-off-by: Jukka Laitinen <[email protected]>
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risc-v/mpfs: serial: fix uart closing
Don't turn off FIC3 clk which would terminate all other peripherals depending on it. Also add a few missing undefs. Signed-off-by: Eero Nurkkala <[email protected]>
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Change MPFS_FPGA_UARTx_BASE addresses to 4k aligned as per new FPGA i…
…mage Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_timerisr.c: Partially revert common mtime d…
…river change Revert: commit 1975878 Author: Huang Qi <[email protected]> Date: Mon Apr 11 18:42:24 2022 +0800 arch/risc-v: Apply common mtime driver to mtime based chps Signed-off-by: Huang Qi <[email protected]> As this breaks the systick Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs: Make mpfs_hart_index2id table modifiable by boo…
…tloader This is actually the same table as entrypoints, so just use the same data, which can be set before booting any of the harts Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_opensbi.c: Fix conflicting datatypes define…
…d by NuttX vs. opensbi Signed-off-by: Jukka Laitinen <[email protected]>
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mpfs_opensbi_utils.S: relocate OpenSBI into l2zerodevice
This loads the OpenSBI from eNVM into the zerodevice. Signed-off-by: Eero Nurkkala <[email protected]>
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arch/risc-v/src/mpfs: Set USB DMA upper addr offset
Use a configuration register to set the upper address lines [37:32] for USB DMA engine. Signed-off-by: Jani Paalijarvi <[email protected]>
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risc-v/mpfs: emmcsd: deny unaligned access
Don't allow unaligned access with the DMA requests. Return -EFAULT in case the provided address is unaligned. Signed-off-by: Eero Nurkkala <[email protected]>
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[REVERTME] riscv_addrenc.c: Add more heap, if TLS_ALIGNED is set
The TLS alignment requires more room in the stack, which means more _initial_ heap is required to accomodate the stack. Why 2x TLS_MAXSTACK ? No idea. This is a temporary fix, like the +1 page extra above.
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arch/risc-v/src/mpfs/mpfs_ddr.c: Add read dq/dqs eye centering test
After read training, check also that the eye is centered properly. Sometimes after the training the width is long enough, but it is not centered. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Clean up the TXDLY verify step
Just verify that the delay for the selected clock != 0 Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Fix CA training verify step
Corrections to CA training verify step. The original copied from HSS didn't make sense in all aspects: - The check is not per lane, so it should be out of the "for (lane_sel" loop. - The check wasn't proper. The expected outcome is just a vector of increasing numbers separated enough Signed-off-by: Jukka Laitinen <[email protected]>
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risc-v/mpfs: usb: fix fierce cpu polling if remote closes
If the remote end just closes an endpoint and no longer handles it, the system is prone to intensive cpu polling via mpfs_write_tx_fifo() especially if the device side doesn't know a thing about what the remote did. Fix this by marking the EP as dead, which will skip all writes causing unnecessary polling. The EP is back in business if the remote end sends some data (rx) or the connection is re-established. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: usb: don't try nonexistent ep int flags
Currently the irq handler checks many reserved bits, which is a waste of resources: 1. pending_rx_ep bit 0 is reserved (always 0) 2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4 defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the rest are reserved Fix this by checking only the relevant bits. Signed-off-by: Eero Nurkkala <[email protected]>
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net: rpmsgdrv.c: prevent potential danger
Provide support for NET_RPMSG_TRANSFER only: "It is recommended to drop all messages with commands other than NET_RPMSG_TRANSFER in function net_rpmsg_drv_ept_cb() of the flight controller." Signed-off-by: Eero Nurkkala <[email protected]>
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fix MPFS_ETHMAC_LP/HPWORK flags
Set HPWORK as default workqueue for eth ISR work
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risc-v/mpfs: emmcsd: enforce HS DDR mode
Previously, address 0x03b70000u was written with shift bits that only changed the bit width, not the mode. HS mode is changed via 0x03B90100, which is required, according to Jedec specs, for DDR mode. HS mode was not applied before. Enforce DDR mode (50 MHz) for now. The real boost, however, comes from removing the DMA limitation at 0x08xxxxxx address space, which now seems unnecessary. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: ddr: lock segmentation registers
Set the LOCKED bit when the final ddr segmentatition is in place. Otherwise the system is prone to potential security issues if the config is altered later. Once the LOCKED bit is set, the register may no longer be changed. Signed-off-by: Eero Nurkkala <[email protected]>
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build.yml: Modify the build config
Remove unnecessary junk, just build icicle (we don't care about the rest)
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build.yml: Add ssrc board matrix for arm and risc-v
Don't use the upstream build targets
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[HACK] cstdlib: Forward malloc et. al. to kmm_malloc, if __KERNEL__
This is the only way to get the external module "uavcanlib" to work inside the px4 kernel. If an alternate solution, e.g. moving uavcanlib to user space is implemented this hack should be removed.
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mpfs_mpucfg.h: Add missing MPUCFG registers
Now all registers are defined
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risc-v/mpfs: add tamper detection support
This adds support for detecting various tamper events. The interrupt handler makes noise at every detection. Perhaps easiest test is to attach JTAG debugger. TAMPER_TESTS -define has some nonexisting (not in repos) calls, perhaps could remove it alltogether. Signed-off-by: Eero Nurkkala <[email protected]>
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[REVERTME - useless] libs/libc/machine/risc-v/arch_elf.c: Minor optim…
…ization to _calc_imm Signed-off-by: Jukka Laitinen <[email protected]>
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mpfs_mpu: Add driver to set MPUCFG registers
MPUCFG registers are used to enforce memory protection for DMA master devices.
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mpfs_usb.c: Remove PMPCFG configuration from the driver
This is not the right place to modify DMA memory protection values. Why not? These are designed to protect other AMP mode instances. Opening the entire SoC's memory for the USB DMA kind of defeats this purpose. Also, the driver cannot know how to configure these registers correctly, only opening up the whole SoC "works".
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mpfs_corespi: Fix firing of stale interrupt after warm reset
After warm reset the interrupt source in the HW block is not explicitly cleared, thus once the interrupt source is enabled the old / stale interrupt fires immediately. This causes a DEBUGASSERT() failure on line 808 mpfs_spi_unload_rx_fifo: DEBUGASSERT(nwords > 0);
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arch/risc-v/src/mpfs/mpfs_serial.c: Allow switching uart output to co…
…nsole off By setting "isconsole" to false, mpfs_serial stops outputting to console. This can be used to disable output to debug console in low level. Signed-off-by: Jukka Laitinen <[email protected]>
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risc-v/mpfs: i2c: prevent out of bounds read access
priv->msgid may grow past its boundaries, causing struct i2c_msg_s *msg = &priv->msgv[priv->msgid] to read data out of boundaris. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: i2c: perform sanity checks
Replace risky DEBUGASSERT()s with real sanity checks. Also, do a few more checks as the system might occasionally fire an interrupt if the system has been restarted while in middle of an i2c transaction. Yet, modify i2c_transfer() function so that up_disable_irq() is always called at the end to better prevent ill-timed irqs. Signed-off-by: Eero Nurkkala <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Clear I2C_CTRL bits when initializin…
…g/deinitializing bus Ensure that there are no pending state or interrupts in the i2c controller. This removes errors caused by deinitialize/initialize sequences in error cases. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Add more error status codes
Add more error status codes to help debugging in the future. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Correct i2c reset / error recovery
- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block - Use the i2c mutex to protect the reset; in case there are several devices on the same bus, and one of them resets the bus, reset must not occur in the middle of another device's transfer. - Move irq attach to the i2c_init as the irq detach is in i2c_deinit Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Add more i2cerr traces
Add sanity checks for debugging possible errors in the driver. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Recover i2c from pending transaction…
…s in warm boot Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_irq.c: Fix up_irqinitialize for warm reboot
It is possible that a PLIC IRQ is claimed but not completed at warm reset. This occurs at least if there is a fault in the middle of irq handler execution. To recover from such situation, we can complete all IRQ:s in PLIC; this completes any already claimed IRQ, but has no effect on IRQs which are not claimed or not enabled. Signed-off-by: Jukka Laitinen <[email protected]>
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mpfs_mpucfg.c: Add mpfs_mpu_lock()
Add method to lock an MPUCFG entry. Locking means the value of the register cannot be changed until the SoC is reset.
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fs/shmfs: Fix CONFIG_FS_SHM -> CONFIG_FS_SHMFS
The macro was wrong
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fs/shmfs: Fix stat() system call for shmfs object
Set i_size for shmfs objects
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arch/addrenv: Add utility function to wipe one page
up_addrenv_page_wipe can be used to wipe a single page of memory.
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shmfs/shmfs_alloc. Fix POSIX violation for shmfs_truncate
When shmfs_truncate is called, it uses shmfs_alloc_object to create the physical backing for the shm file. However, the allocated physical memory returned by mm_pgalloc is not cleared when CONFIG_BUILD_KERNEL is set, which is a clear POSIX violation: https://pubs.opengroup.org/onlinepubs/9699919799/functions/truncate.html "If the file was previously shorter than length, its size is increased, and the extended area appears as if it were zero-filled." For FLAT and PROTECTED modes zalloc is used, so the violation affects KERNEL mode only.
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openamp: Fix void pointer arithmetic in openamp to remove compilation…
… warnings Signed-off-by: Jukka Laitinen <[email protected]>
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[BACKPORT] net:Add support for multi PHY
Support runtime phy selection based on a list supplied by board.h For Example: #define BOARD_ETH0_PHY_LIST \ { \ "LAN8742A", \ MII_PHYID1_LAN8742A, \ MII_PHYID2_LAN8742A, \ MII_LAN8740_SCSR, \ 0, \ 0xffff, \ MII_LAN8720_SPSCR_10MBPS, \ MII_LAN8720_SPSCR_100MBPS, \ MII_LAN8720_SPSCR_DUPLEX, \ 22 \ }, \ { \ "TJA1103", \ MII_PHYID1_TJA1103, \ MII_PHYID2_TJA1103, \ 0xffff, \ 18, \ 0xffff, \ 0 , \ MII_LAN8720_SPSCR_100MBPS, \ MII_LAN8720_SPSCR_DUPLEX, \ 45, \ }, \
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[BACKPORT] imxrt:ENET Use multi PHY
Allow a board to specify a list of PHYs. Then use this list, at run-time, to select and use the PHY populated on the board.
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Commits on Feb 13, 2024
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boards/risc-v/mpfs/icicle: Normalize standalone and canfd target defc…
…onfigs Signed-off-by: Jukka Laitinen <[email protected]>
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Revert "opensbi: update to contain shrinked version"
This reverts commit c87ad9f.
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Revert "opensbi: Take SBI version that removes console into use"
This reverts commit 1870a5c.
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Revert "arch/risc-v/src/opensbi/Make.defs: Switch opensbi to the nutt…
…x/size optimized version in tiiuae repo" This reverts commit cd75eb6.
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Replace opensbi with tiiuae version
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/arm/src/imxrt/imxrt_start.c: Clear CONTROL register at start to …
…make sure we use MSP as the stack pointer When entering the function from an external bootloader, the CPU could be using PSP. But the following code expects MSP to be in use. Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Mar 13, 2024
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Revert "net/can, net/devif: fix CAN RX/TX iob free semcount runaway i…
…ssue" This reverts commit ac2c321.
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net/can: Release IOB when failed to queue in datahandler
If we just clear the IOB when failed to queue, we'll leak it. Signed-off-by: Zhe Weng <[email protected]>
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net/can/can_callback.c: Take the timestamp size into account in "buflen"
In case CONFIG_NET_TIMESTAMP is enabled, subtract the timestamp size from the buflen Signed-off-by: Jukka Laitinen <[email protected]>
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net/devif/devif_send.c: Don't update the pktlen to 0
If pktlen is 0, there is no need to update Signed-off-by: Jukka Laitinen <[email protected]>
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net/can/can_recvmsg.c: Remove IOB trimming as useless, can frames can…
… always fit in one IOB Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_fpga_canfd.c: Fix a race condition with dev…
…if_poll Signed-off-by: Jukka Laitinen <[email protected]>
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net/can/can_recvmsg.c: Cleanup can_readahead
It is better to just atomically remove the iob from the readahead queue first, and only after that work on the iob. Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Mar 15, 2024
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arch/risc-v/src/mpfs/mpfs_fpga_canfd.c: Improve interrupt and error h…
…andling - Remove unnecessary looping in the interrupt handling - Recover properly from the rx overflow error - Check the RXMOF bit always to sychrnonize the RX frames to recover from any errors - Clear the interrupts in a single place after the irq handler is finished Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_fpga_canfd.c: Enable error interrupts only …
…when in ERROR_ACTIVE state Having error interrupts enabled while in ERROR_PASSIVE will cause interrupt storms, for example bus error would be always asserted if the can is / gets disconnected. Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Mar 21, 2024
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sched/group/group_killchildren.c: Force-cancel children if parent is …
…force-cancelled There is no point in waiting for children to exit if the parent is force-cancelled Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/common/riscv_exception.c: Just _exit the user task ca…
…using an exception We shouldn't panic the kernel when a user task excepts, we can just kill the user task and it's children. Do this by returning to _exit() in kernel context. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/common/supervisor/riscv_perform_syscall.c: Record the…
… currently running task in risc-v syscall If a context switch occurs in syscall, the g_running_task need to be recorded for assert logic. This copies the logic from arm platforms Signed-off-by: Jukka Laitinen <[email protected]>
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arm64_internal.h: Expose prototype for arm64_lowputc
Useful procedure in many places.
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arm64/imx9: Add support for imx9 series SoMs, imx93 implemented
Adds support for NXP i.MX9-series System-on-Module chips. - Support for i.MX93 is added - CPU is Cortex A55 / ARMv8.2A - The chip also contains a Cortex M33, but no support is provided - Supported drivers include lpuart only for now
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arm64/imx9: Add board for imx93-evk
Adds board definition for imx93-evk board - Support for the Cortex-A55 core in i.MX93, support for the Cortex-M33 core is _not_ provided - "nsh" profile is provided, this includes a minimalistic feature set which boots the SoM to nsh console - A bootloader is required, u-boot has been tested
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arm64/imx9: Add JLinkScript for imx93-evk
This is needed, as it contains the DAP addresses.
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Commits on Mar 22, 2024
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arch/arm64/src/common: Remove void * arithmetic
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/arm64: Add the head obj to libarch.a as well
On other platforms libarch.a contains the head object. Some projects depend on this fact so let's provide the head object in the archive here as well.
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stm32f7/stm32_foc.c: Set .info_get to foc_lower_ops
This fixes build error (Werror): Error: chip/stm32_foc.c:1918:12: error: 'stm32_foc_info_get' defined but not used [-Werror=unused-function] 1918 | static int stm32_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info) | ^~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors
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Commits on Mar 25, 2024
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arm64_head.S: Add explicit input section for __start
As __start must be placed at a precise location, a separate, explicit input section is needed to guarantee this. Why is this an issue ? NuttX uses --entry=__start which puts __start in its correct location, but out-of-tree builds won't work, so it more robust to use an explicit section for the startup code and enforce its placement in the linker script.
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Commits on Apr 4, 2024
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imx9_clockconfig.c: Add way to query clock frequency
The frequency of a clock source is stored in a LUT. Currently the LUT contains the PLL frequencies set by the boot ROM code.
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arm64/imx9: Add GPIO, IOMUX and external interrupt support
This adds memory mapped registers and drivers for digital I/O.
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arch/arm64/src/imx9: Flex-IO based PWM driver for imx9
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for generating PWM period and the rest of the timers to generate PWM duty cycles. This means that the period has to be the same for every PWM generated from one FLEXIO block, but this way we can get 16-bit resolution for the PWM signals. For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means that by using this driver one can get 7 PWM outputs from one block. This driver can be later extended to have configuration options to use all 8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by using an external trigger from an LPIT. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/arm64/include/imx9/imx93_irq.h: Define IRQ_USBx interrupt numbers
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h: Clean up some b…
…ase address macros Signed-off-by: Jukka Laitinen <[email protected]>
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arch/arm64/src/imx9: Add imx9 usb device driver
This is a modified version from imxrt driver, which has the same controller. Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Apr 5, 2024
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arch/arm64/src/imx9: Add TPM based PWM driver for IMX9
Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Apr 8, 2024
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arch/arm64/src/imx9/imx9_flexio_pwm.c: Fix wrong input scale and puls…
…e width Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Apr 9, 2024
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Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Apr 15, 2024
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build(deps): bump actions/upload-artifact from 3 to 4
Bumps [actions/upload-artifact](https://github.com/actions/upload-artifact) from 3 to 4. - [Release notes](https://github.com/actions/upload-artifact/releases) - [Commits](actions/upload-artifact@v3...v4) --- updated-dependencies: - dependency-name: actions/upload-artifact dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <[email protected]>
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