Make FP reg operand notation consistent (riscv#398)

Fixes riscv#395 using the same notation from the RISC-V unprivileged ISA spec --------- Signed-off-by: Tariq Kurd <[email protected]> Co-authored-by: Tariq Kurd <[email protected]>
tariqkurd-repo · Oct 9, 2024 · c335d70 · c335d70
1 parent f312cf0
commit c335d70
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Showing 9 changed files with 9 additions and 9 deletions.
diff --git a/src/insns/wavedrom/c-clc-clcsp.adoc b/src/insns/wavedrom/c-clc-clcsp.adoc
@@ -16,7 +16,7 @@
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C2=10']},
-  {bits: 5, name: 'fs2',    type: 4, attr: ['5','src',]},
+  {bits: 5, name: 'rs2',    type: 4, attr: ['5','src',]},
   {bits: 6, name: 'imm',    type: 3, attr: ['6','offset[5:3|8:6]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3','cap rv64: C.LCSP=001']},
 ], config: {bits: 16}}

diff --git a/src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc b/src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc
@@ -3,7 +3,7 @@
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C2=10']},
-  {bits: 5, name: 'fs2',    type: 4, attr: ['5','src']},
+  {bits: 5, name: 'rs2',    type: 4, attr: ['5','src']},
   {bits: 6, name: 'imm',    type: 3, attr: ['6','offset[5:3|8:6]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg: C.FLDSP=001', 'cap rv32: C.FLDSP=001']},
 ], config: {bits: 16}}

diff --git a/src/insns/wavedrom/c-sp-load-css-dp.adoc b/src/insns/wavedrom/c-sp-load-css-dp.adoc
@@ -3,7 +3,7 @@
 ....
 {reg: [
   {bits: 2, name: 'op',     attr: ['2', 'C0=00'], type: 8},
-  {bits: 3, name: 'frd`',    attr: ['3', 'dest'], type: 3},
+  {bits: 3, name: 'rd`',    attr: ['3', 'dest'], type: 3},
   {bits: 2, name: 'imm',    attr: ['2', 'offset[7:6]'], type: 2},
   {bits: 3, name: 'rs1`/cs1`',   attr: ['3', 'base'], type: 2},
   {bits: 3, name: 'imm',    attr: ['3', 'offset[5:3]'], type: 3},

diff --git a/src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc b/src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc
@@ -4,7 +4,7 @@
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C2=10']},
   {bits: 5, name: 'uimm',   type: 3, attr: ['5','offset[4:2|7:6]']},
-  {bits: 5, name: 'frd',    type: 4, attr: ['5','src']},
+  {bits: 5, name: 'rd',     type: 4, attr: ['5','src']},
   {bits: 1, name: 'uimm[5]',type: 3, attr: ['1','offset[5]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FLWSP=011']},
 ], config: {bits: 16}}

diff --git a/src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc b/src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc
@@ -4,7 +4,7 @@
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C2=10']},
-  {bits: 5, name: 'fs2',    type: 4, attr: ['5','src']},
+  {bits: 5, name: 'rs2',    type: 4, attr: ['5','src']},
   {bits: 6, name: 'imm',    type: 3, attr: ['6','offset[5:3|8:6]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg C.FSDSP=101', 'cap rv32: C.FSDSP=101']},
 ], config: {bits: 16}}

diff --git a/src/insns/wavedrom/c-sp-store-css-fp-dp.adoc b/src/insns/wavedrom/c-sp-store-css-fp-dp.adoc
@@ -4,7 +4,7 @@
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C0=00']},
-  {bits: 5, name: 'fs2',    type: 4, attr: ['5','src']},
+  {bits: 5, name: 'rs2',    type: 4, attr: ['5','src']},
   {bits: 6, name: 'imm',    type: 3, attr: ['6','offset[5:3|8:6]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg C.FSD=101', 'cap rv32: C.FSD=101']},
 ], config: {bits: 16}}

diff --git a/src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc b/src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc
@@ -4,7 +4,7 @@
 ....
 {reg: [
   {bits: 2, name: 'op',     type: 8, attr: ['2','C2=10']},
-  {bits: 5, name: 'fs2',    type: 4, attr: ['5','src']},
+  {bits: 5, name: 'rs2',    type: 4, attr: ['5','src']},
   {bits: 6, name: 'imm',    type: 3, attr: ['6','offset[5:2|7:6]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FSWSP=111']},
 ], config: {bits: 16}}

diff --git a/src/insns/wavedrom/fpload.adoc b/src/insns/wavedrom/fpload.adoc
@@ -3,7 +3,7 @@
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP=0000111'],  type: 8},
-  {bits: 5,  name: 'frd',       attr: ['5','dest'],     type: 2},
+  {bits: 5,  name: 'rd',        attr: ['5','dest'],     type: 2},
   {bits: 3,  name: 'width',     attr: ['3','FLD=011','FLW=010', 'FLH=001'],    type: 8},
   {bits: 5,  name: 'rs1/cs1',   attr: ['5','base'],     type: 4},
   {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'],   type: 3},

diff --git a/src/insns/wavedrom/fpstore.adoc b/src/insns/wavedrom/fpstore.adoc
@@ -6,7 +6,7 @@
   {bits: 5,  name: 'imm[4:0]',  attr: ['5','offset[4:0]'],   type: 3},
   {bits: 3,  name: 'width',     attr: ['3','FSD=011','FSW=010', 'FSH=001'],    type: 8},
   {bits: 5,  name: 'rs1/cs1',   attr: ['5','base'],     type: 4},
-  {bits: 5,  name: 'fs2',       attr: ['5','src'],      type: 4},
+  {bits: 5,  name: 'rs2',       attr: ['5','src'],      type: 4},
   {bits: 7,  name: 'imm[11:5]', attr: ['7','offset[11:5]'],   type: 3},
 ]}
 ....