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Make FP reg operand notation consistent #398

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merged 2 commits into from
Oct 3, 2024
Merged

Make FP reg operand notation consistent #398

merged 2 commits into from
Oct 3, 2024

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andresag01
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@andresag01 andresag01 commented Oct 2, 2024 •
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Fixes #395 using the same notation from the RISC-V unprivileged ISA spec

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tariqkurd-repo commented Oct 2, 2024 •
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you've changed the assembly syntax which does use the f notation
it is a bugbear of mine that risc-v use integer src/dsts for fpu instructions, it makes their spec much harder to use
but certainly the encoding should use rd, rs1, rs2 to be consistent

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tariqkurd-repo reviewed Oct 2, 2024
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can we double check the RISC-V assembly syntax? I'm pretty sure it uses f numbers

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2553695 
switch asm syntax back

Signed-off-by: Tariq Kurd <[email protected]>
@tariqkurd-repo tariqkurd-repo self-requested a review October 2, 2024 17:33
@tariqkurd-repo tariqkurd-repo merged commit f72d917 into riscv:main Oct 3, 2024
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tariqkurd-repo added a commit to tariqkurd-repo/riscv-cheri that referenced this pull request Oct 9, 2024
@andresag01 @tariqkurd-repo
Make FP reg operand notation consistent (riscv#398)
c335d70 
Fixes riscv#395 using the same notation from the RISC-V unprivileged ISA spec

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Signed-off-by: Tariq Kurd <[email protected]>
Co-authored-by: Tariq Kurd <[email protected]>
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@tariqkurd-repo tariqkurd-repo tariqkurd-repo approved these changes

@arichardson arichardson arichardson approved these changes

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Floating point loads inconsistent mnemonic
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@andresag01 @tariqkurd-repo @arichardson