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WIP: Implement RV32C instruction decoder #3

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WIP: Implement RV32C instruction decoder #3

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6932a6b
Modified .gitignore for testing files
Jan 4, 2021
fbbe1d7
Revise PC, Add Inst. Table & Inst. Distinguishment
ccs100203 Jan 4, 2021
8874ab5
Add Decoding Func., Inst. Templates & A Few Func. Definitions
ccs100203 Jan 5, 2021
9b778a4
Modified Makefile to support debug build & RV32C
Jan 5, 2021
8ab1561
Implemented c_op_lwsp(), Wrapped RV32F Instructions.
Jan 5, 2021
81b093a
Implemented `c_op_lw()`, Added debug messages
Jan 5, 2021
bc04ca4
Inplemented CJ-type instructions.
Jan 6, 2021
147da15
Modified target degug to make sure rebuild
Jan 6, 2021
5907732
Implemented CJ-type inst.
Jan 6, 2021
5c8b4a7
Revise Debug Function
ccs100203 Jan 7, 2021
00bc59c
Add Define NULL in Compressed Inst.
ccs100203 Jan 7, 2021
8a505f0
Revise Compressed Float Inst. Definition
ccs100203 Jan 7, 2021
505e139
Implement C.LUI & C.ADDI16SP Inst.
ccs100203 Jan 7, 2021
5b3491e
Implemented CB-type Inst, Fixed Few Sign-Extension Bugs
Jan 8, 2021
2ff89bb
Implemented c.sw Instruction
Jan 8, 2021
ed15df6
Implemented c_op_slli()
Jan 8, 2021
9379eeb
Implement c.srli, c.srai, c.slli c.andi Inst.
Jan 8, 2021
15573d4
Relocated some debug print
Jan 8, 2021
c153524
Implemented c.sub, c.and, c.xor, c.or Inst.
Jan 8, 2021
51ed5e1
Implemented c.mv, c.add Inst.
Jan 8, 2021
8e338d7
Fix Inst. Ebreak Function
ccs100203 Jan 15, 2021
36deb34
Remove Unuseful Comment
ccs100203 Jan 15, 2021
5640c17
Revise Coding Format
ccs100203 Jan 16, 2021
69ba1e1
Remove Useless Comment
ccs100203 Jan 16, 2021
6da4329
Revise Address Validation
ccs100203 Jan 19, 2021
a0d65f3
Remove Debug Setting & Transfer to Other Branch
ccs100203 Jan 19, 2021
228b6e3
Revise Code Format
ccs100203 Jan 20, 2021
76e7d92
Rename a Directory in .gitignore
ccs100203 Jan 20, 2021
70fe234
Compact the If Condition & Add Some Comments
ccs100203 Jan 20, 2021
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2 changes: 2 additions & 0 deletions .gitignore
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Expand Up @@ -2,3 +2,5 @@ build/DOOM1.WAD*
build/rv32emu
*.o
*.o.d
tests/
.vscode
1 change: 1 addition & 0 deletions Makefile
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Expand Up @@ -7,6 +7,7 @@ CFLAGS += -D ENABLE_Zicsr
CFLAGS += -D ENABLE_Zifencei
CFLAGS += -D ENABLE_RV32A
CFLAGS += -D DEFAULT_STACK_ADDR=0xFFFFF000
CFLAGS += -D ENABLE_RV32C

# Experimental SDL oriented system calls
CFLAGS += -D ENABLE_SDL
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6 changes: 5 additions & 1 deletion io.c
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Expand Up @@ -70,7 +70,11 @@ uint32_t memory_read_str(memory_t *m, uint8_t *dst, uint32_t addr, uint32_t max)
uint32_t memory_read_ifetch(memory_t *m, uint32_t addr)
{
const uint32_t addr_lo = addr & mask_lo;
assert((addr_lo & 3) == 0);
#ifdef ENABLE_RV32C
assert((addr_lo & 1) == 0);
#else
assert((addr_lo & 3) == 0);
#endif

chunk_t *c = m->chunks[addr >> 16];
assert(c);
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