WIP: Implement RV32C instruction decoder #3
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In `riscv_private.h`: - Add variable `inst_len` in structure `riscv_t` to record length of current instruction - Add mask for compressed instruction opcode In `riscv.c`: - Add function table `c_opcodes`, defined `NULL` - Modify `rv_step()` to process compressed instructions
In riscv_private.h: - Add instruction decoding function & revise masks In io.c: - revise address check In riscv.c: - Add compressed instruction templates - Add register checking function - Implement c_op_addi(), c_op_swsp(), c_op_addi4spn(), c_op_li()
In `Makefike`: - Added target `debug`, used to enable debug functions when building - Added `ENABLE_RV32C` flag
In `riscv.c`: - Implemented `c_op_lwsp()` for c.lwsp instruction - Moved F-Extension related functions into #ifdef wrappers for future implementation
In `riscv.c`: - Added debug message "Entered c.XXX" to inform which function is called - Implemented `c_op_lw()` - Removed RV64 and RV128 only instructions - Moved more RV32F related instruction into #define wrapper - Added temporary variable to some function to reduce line width
In `riscv.c`: - Inplemented `c_op_j()` , `c_op_jal()`
In `riscv.c` - Added `c_op_cjtype()` - Added instruction unaligned exception check for PC modifying instructions In `riscv_private.h`: - Removed unneeded masks TODO: - Find out rules for instruction functions' (op_XXX) return value
In riscv.c: - Modify print_register() to being a macro
In risc.c: - Add compressed instruction define NULL
In riscv.c: - Extract RV32C.F from RV32C block
In riscv.c: - Implement c_op_lui function - Revise a few sign-extended immediates
in `riscv.c`: - Implemented c_bneq(), c_beqz() - Fixed overlooked sign extension bugs in `riscv-private.c`: - Added c_dec_cbtype_imm(), c_dec_cjtype_imm()
In `riscv.c`: - Added c_op_sw();
in `riscv.c`: - Added c_op_slli()
In `riscv.c`: - Started implementing c_op_misc_alu() - Added c_op_slli() - Added c_op_srli() - Added c_op_srai() - Added c_op_andi() TODO: - Change name of c_op_cr to fit future modification (add C.MV and C.ADD, etc.)
In `riscv.c`: - Revised c_op_cr() to fit all 5 instructions: + c.add + c.mv + c.jr + c.jalr + c.ebreak (Debug message only) - Changed return value to false wherever PC might jump
In riscv.c: - Add the ebreak function
In riscv.c: - remove unuseful comment
jserv
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jserv
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Jan 15, 2021
jserv
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Jan 15, 2021
jserv
reviewed
Jan 15, 2021
jserv
reviewed
Jan 15, 2021
jserv
reviewed
Jan 15, 2021
ccs100203
changed the title
Using clang-format to format the code.
Remove useless comment in .gitignore.
Adding a condition, if RV is enabled, the addr_io check will be changed into 1.
The debug setting and dumping is transferred to 'debug' branch.
jserv
reviewed
Jan 20, 2021
jserv
reviewed
Jan 20, 2021
jserv
reviewed
Jan 20, 2021
Reactivate clang in riscv_private.h, make it can be formated by clang.
Rename test/ to tests/.
Rewrite c_op_beqz & c_op_bnez into a ternary operator.
|
Drop in favor of #11 |
vacantron
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to vacantron/rv32emu
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Dec 14, 2024
-fsanitize=address report when CTRL+a x exiting:
=================================================================
==297977==ERROR: LeakSanitizer: detected memory leaks
Direct leak of 23400 byte(s) in 117 object(s) allocated from:
#0 0x761b706fd340 in calloc ../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:77
#1 0x633ad9c5e310 in block_translate src/emulate.c:649
sysprog21#2 0x633ad9c5e310 in block_find_or_translate src/emulate.c:865
sysprog21#3 0x633ad9c5e310 in rv_step src/emulate.c:1029
sysprog21#4 0x633ad9c5e310 in rv_run src/riscv.c:498
sysprog21#5 0x633ad9c5e310 in main src/main.c:279
Direct leak of 3136 byte(s) in 125 object(s) allocated from:
#0 0x761b706fd9c7 in malloc ../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:69
#1 0x633ad9c5fea4 in match_pattern src/emulate.c:767
sysprog21#2 0x633ad9c5fea4 in block_find_or_translate src/emulate.c:872
sysprog21#3 0x633ad9c5fea4 in rv_step src/emulate.c:1029
sysprog21#4 0x633ad9c5fea4 in rv_run src/riscv.c:498
sysprog21#5 0x633ad9c5fea4 in main src/main.c:279
Register a clean up callback, async_block_clear() to free all the
allocated memory fix this when emulator exits.
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RISC-V Compressed Instruction Support
We implemented the compressed instructions for rv32emu-next.
Moreover, We still don't support RV32C.F instructions.
However, it doesn't yet pass the compliance test.