Fix for issue chipsalliance#826, illegal rs1 in C_JALR

Signed-off-by: Henrik Fegran <[email protected]>
silabs-hfegran · Jul 25, 2022 · 88dae63 · 88dae63
1 parent 4860da2
commit 88dae63
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/isa/riscv_compressed_instr.sv b/src/isa/riscv_compressed_instr.sv
@@ -314,7 +314,7 @@ class riscv_compressed_instr extends riscv_instr;
       C_EBREAK:
         binary = $sformatf("%4h", {get_func3(), 1'b1, 10'b0, get_c_opcode()});
       C_JALR:
-        binary = $sformatf("%4h", {get_func3(), 1'b1, 10'b0, get_c_opcode()});
+        binary = $sformatf("%4h", {get_func3(), 1'b1, rs1, 5'b0, get_c_opcode()});
       C_ADD:
         binary = $sformatf("%4h", {get_func3(), 1'b1, rd, rs2, get_c_opcode()});
       C_SDSP: