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Sanitise linker scripts #17
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ben-marshall
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Aug 18, 2020
- See #23. Working verilator build and running out of ROM. - Need to implement simulator appropriate UART. - See #17. FSBL now uses scarv-cpu core complex linker script. On branch scarv/skywater/dev Changes to be committed: modified: extern/scarv-cpu modified: flow/gtkwave/scarv-soc.gtkw modified: flow/selfcheck/Makefile.in modified: flow/verilator/Makefile.in new file: flow/verilator/manifest-soc-rtl.txt new file: flow/verilator/manifest-soc-tb.txt deleted: flow/verilator/scarv-soc-rtl.manifest new file: flow/verilator/scarv-soc-tb.cmd deleted: flow/verilator/scarv-soc-testbench.manifest new file: rtl/gpio/gpio_top.sv new file: rtl/soc/scarv_soc.sv deleted: rtl/soc/scarv_soc.v new file: rtl/soc/scarv_soc_periph_top.sv new file: rtl/uart/uart_top.sv
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There are currently 4 different linker scripts used in the project:
flow/selfcheck/boot-link.ldflow/selfcheck/test-link.ldsrc/examples/share/link.ldsrc/fsbl/link.ldThese should really be combined into just two:
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