skw: Working on new soc architecture.

- See #23. Working verilator build and running out of ROM.

  - Need to implement simulator appropriate UART.

- See #17. FSBL now uses scarv-cpu core complex linker script.

 On branch scarv/skywater/dev
 Changes to be committed:
	modified:   extern/scarv-cpu
	modified:   flow/gtkwave/scarv-soc.gtkw
	modified:   flow/selfcheck/Makefile.in
	modified:   flow/verilator/Makefile.in
	new file:   flow/verilator/manifest-soc-rtl.txt
	new file:   flow/verilator/manifest-soc-tb.txt
	deleted:    flow/verilator/scarv-soc-rtl.manifest
	new file:   flow/verilator/scarv-soc-tb.cmd
	deleted:    flow/verilator/scarv-soc-testbench.manifest
	new file:   rtl/gpio/gpio_top.sv
	new file:   rtl/soc/scarv_soc.sv
	deleted:    rtl/soc/scarv_soc.v
	new file:   rtl/soc/scarv_soc_periph_top.sv
	new file:   rtl/uart/uart_top.sv