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Rollup of 10 pull requests #131785

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wants to merge 27 commits into from
Closed

Rollup of 10 pull requests #131785

wants to merge 27 commits into from

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Urgau
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@Urgau Urgau commented Oct 16, 2024

Successful merges:

r? @ghost
@rustbot modify labels: rollup

Create a similar rollup

beetrees and others added 27 commits October 13, 2024 00:44
Two macros are exactly the same.
It is possible to link libunwind and use the normal backtrace code, but it fails
to symbolize stack traces. I investigated and could get the list of instruction
pointers and symbol names, but I'm not sure how to use the dwarf info to map
from instruction pointer to source location. In any case, fixing this is
probably not a high priority.

See rust-lang#131738
Pass end position of span through inline ASM cookie

Before this PR, only the start position of the span was passed though the inline ASM cookie to diagnostics. LLVM 19 has full support for 64-bit inline ASM cookies; this PR uses that to pass the end position of the span in the upper 32 bits, meaning inline ASM diagnostics now point at the entire line the error occurred on, not just the first character of it.
…stebank

Don't check unsize goal in MIR validation when opaques remain

Similarly to `mir_assign_valid_types`, let's just skip when there are opaques. Fixes rust-lang#130921.
… r=ytmimi

Rustfmt `for<'a> async` correctly

In rust-lang#127054, we decided to move the trait bound modifier for `async for<'a> Fn()`  to `for<'a> async Fn()`. This wasn't adjusted in rustfmt, so this PR implements that. It also requires consolidating the bound formatting into the `Rewrite` impl for `PolyTraitRef`.

Fixes rust-lang#131649
…er-out-2, r=notriddle

Delay ambiguous intra-doc link resolution after `Cache` has been populated

Fixes rust-lang#130233.

I was getting nowhere with rust-lang#130278. I took a wrong turn at some point and ended making way too many changes so instead I started again back from 0 and this time it worked out as expected.

r? ``@notriddle``
Refactor some `core::fmt` macros

While looking at the macros in `core::fmt`, find that the macros are not well organized. So I created a patch to fix it.

[`core/src/fmt/num.rs`](https://github.com/rust-lang/rust/blob/master/library/core/src/fmt/num.rs)
*  `impl_int!` and `impl_uint!` macro are **completly** same. It would be better to combine for readability
* `impl_int!` has a problem that the indenting is not uniform. It has unified into 4 spaces
* `debug` macro in `num` renamed to `impl_Debug`, And it was moved to a position close to the `impl_Display`.

[`core/src/fmt/float.rs`](https://github.com/rust-lang/rust/blob/master/library/core/src/fmt/float.rs)
[`core/src/fmt/nofloat.rs`](https://github.com/rust-lang/rust/blob/master/library/core/src/fmt/nofloat.rs)
* `floating` macro now receive multiple idents at once. It makes the code cleaner.
* Modified the panic message more clearly in fallback function of `cfg(no_fp_fmt_parse)`
…ve, r=lcnr

Rename `can_coerce` to `may_coerce`, and then structurally resolve correctly in the probe

We need to structurally resolve the lhs and rhs of the coercion. Also, renaming the method so it's less ambiguous about what it's doing... the word "may" gives more clear signal that it has false positives imo.

r? lcnr
…jieyouxu

Unify `secondary_span` and `swap_secondary_and_primary` args in `note_type_err`

Tiny tweak b/c working w `note_type_err` is kinda a mess.
…e-tests, r=jieyouxu

Emscripten: Xfail backtrace ui tests

It is possible to link libunwind and use the normal backtrace code, but it fails to symbolize stack traces. I investigated and could get the list of instruction pointers and symbol names, but I'm not sure how to use the dwarf info to map from instruction pointer to source location. In any case, fixing this is not a high priority.

See rust-lang#131738

r?jieyouxu
…s_by_ref, r=jieyouxu

Fix trivially_copy_pass_by_ref in stable_mir

Hi,

This PR fixes the following clippy warnings

```
warning: this argument (8 byte) is passed by reference, but would be more efficient if passed by value (limit: 8 byte)
    --> compiler/stable_mir/src/mir/body.rs:1042:34
     |
1042 |     fn subslice_ty(ty: Ty, from: &u64, to: &u64, from_end: &bool) -> Result<Ty, Error> {
     |                                  ^^^^ help: consider passing by value instead: `u64`
     |
     = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#trivially_copy_pass_by_ref
     = note: requested on the command line with `-W clippy::trivially-copy-pass-by-ref`

warning: this argument (8 byte) is passed by reference, but would be more efficient if passed by value (limit: 8 byte)
    --> compiler/stable_mir/src/mir/body.rs:1042:44
     |
1042 |     fn subslice_ty(ty: Ty, from: &u64, to: &u64, from_end: &bool) -> Result<Ty, Error> {
     |                                            ^^^^ help: consider passing by value instead: `u64`
     |
     = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#trivially_copy_pass_by_ref

warning: this argument (1 byte) is passed by reference, but would be more efficient if passed by value (limit: 8 byte)
    --> compiler/stable_mir/src/mir/body.rs:1042:60
     |
1042 |     fn subslice_ty(ty: Ty, from: &u64, to: &u64, from_end: &bool) -> Result<Ty, Error> {
     |                                                            ^^^^^ help: consider passing by value instead: `bool`
     |
     = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#trivially_copy_pass_by_ref

```

Best regards,
Michal
…, r=jieyouxu

Fix needless_lifetimes in stable_mir

Hi,

This PR fixes the following clippy warning

```
warning: the following explicit lifetimes could be elided: 'a
   --> compiler/stable_mir/src/mir/visit.rs:490:6
    |
490 | impl<'a> PlaceRef<'a> {
    |      ^^           ^^
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_lifetimes
    = note: `#[warn(clippy::needless_lifetimes)]` on by default
help: elide the lifetimes
    |
490 - impl<'a> PlaceRef<'a> {
490 + impl PlaceRef<'_> {
    |
```

Best regards,
Michal
@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue. labels Oct 16, 2024
@rustbot rustbot added T-rustdoc Relevant to the rustdoc team, which will review and decide on the PR/issue. WG-trait-system-refactor The Rustc Trait System Refactor Initiative (-Znext-solver) rollup A PR which is a rollup labels Oct 16, 2024
@Urgau
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Urgau commented Oct 16, 2024

@bors r+ rollup=never p=10

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bors commented Oct 16, 2024

📌 Commit 7d1ff20 has been approved by Urgau

It is now in the queue for this repository.

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Oct 16, 2024
bors added a commit to rust-lang-ci/rust that referenced this pull request Oct 16, 2024
Rollup of 10 pull requests

Successful merges:

 - rust-lang#129181 (Pass end position of span through inline ASM cookie)
 - rust-lang#130989 (Don't check unsize goal in MIR validation when opaques remain)
 - rust-lang#131657 (Rustfmt `for<'a> async` correctly)
 - rust-lang#131691 (Delay ambiguous intra-doc link resolution after `Cache` has been populated)
 - rust-lang#131730 (Refactor some `core::fmt` macros)
 - rust-lang#131751 (Rename `can_coerce` to `may_coerce`, and then structurally resolve correctly in the probe)
 - rust-lang#131753 (Unify `secondary_span` and `swap_secondary_and_primary` args in `note_type_err`)
 - rust-lang#131776 (Emscripten: Xfail backtrace ui tests)
 - rust-lang#131777 (Fix trivially_copy_pass_by_ref in stable_mir)
 - rust-lang#131778 (Fix needless_lifetimes in stable_mir)

r? `@ghost`
`@rustbot` modify labels: rollup
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bors commented Oct 16, 2024

⌛ Testing commit 7d1ff20 with merge a73daed...

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The job x86_64-gnu-llvm-19 failed! Check out the build log: (web) (plain)

Click to see the possible cause of the failure (guessed by this bot)
diff of stderr:

2   --> $DIR/riscv32e-registers.rs:43:11
3    |
4 LL |     asm!("li x16, 0");
+    |           ^^^^^^^^^
6    |
7 note: instantiated into assembly here
7 note: instantiated into assembly here
8   --> <inline asm>:1:5
14   --> $DIR/riscv32e-registers.rs:46:11
15    |
15    |
16 LL |     asm!("li x17, 0");
+    |           ^^^^^^^^^
18    |
19 note: instantiated into assembly here
19 note: instantiated into assembly here
20   --> <inline asm>:1:5
26   --> $DIR/riscv32e-registers.rs:49:11
27    |
27    |
28 LL |     asm!("li x18, 0");
+    |           ^^^^^^^^^
30    |
31 note: instantiated into assembly here
31 note: instantiated into assembly here
32   --> <inline asm>:1:5
38   --> $DIR/riscv32e-registers.rs:52:11
39    |
39    |
40 LL |     asm!("li x19, 0");
+    |           ^^^^^^^^^
42    |
43 note: instantiated into assembly here
43 note: instantiated into assembly here
44   --> <inline asm>:1:5
50   --> $DIR/riscv32e-registers.rs:55:11
51    |
51    |
52 LL |     asm!("li x20, 0");
+    |           ^^^^^^^^^
54    |
55 note: instantiated into assembly here
55 note: instantiated into assembly here
56   --> <inline asm>:1:5
62   --> $DIR/riscv32e-registers.rs:58:11
63    |
63    |
64 LL |     asm!("li x21, 0");
+    |           ^^^^^^^^^
66    |
67 note: instantiated into assembly here
67 note: instantiated into assembly here
68   --> <inline asm>:1:5
74   --> $DIR/riscv32e-registers.rs:61:11
75    |
75    |
76 LL |     asm!("li x22, 0");
+    |           ^^^^^^^^^
78    |
79 note: instantiated into assembly here
79 note: instantiated into assembly here
80   --> <inline asm>:1:5
86   --> $DIR/riscv32e-registers.rs:64:11
87    |
87    |
88 LL |     asm!("li x23, 0");
+    |           ^^^^^^^^^
90    |
91 note: instantiated into assembly here
91 note: instantiated into assembly here
92   --> <inline asm>:1:5
98   --> $DIR/riscv32e-registers.rs:67:11
99    |
99    |
100 LL |     asm!("li x24, 0");
+    |           ^^^^^^^^^
102    |
103 note: instantiated into assembly here
103 note: instantiated into assembly here
104   --> <inline asm>:1:5
110   --> $DIR/riscv32e-registers.rs:70:11
111    |
111    |
112 LL |     asm!("li x25, 0");
+    |           ^^^^^^^^^
114    |
115 note: instantiated into assembly here
115 note: instantiated into assembly here
116   --> <inline asm>:1:5
122   --> $DIR/riscv32e-registers.rs:73:11
123    |
123    |
124 LL |     asm!("li x26, 0");
+    |           ^^^^^^^^^
126    |
127 note: instantiated into assembly here
127 note: instantiated into assembly here
128   --> <inline asm>:1:5
134   --> $DIR/riscv32e-registers.rs:76:11
135    |
135    |
136 LL |     asm!("li x27, 0");
+    |           ^^^^^^^^^
138    |
139 note: instantiated into assembly here
139 note: instantiated into assembly here
140   --> <inline asm>:1:5
146   --> $DIR/riscv32e-registers.rs:79:11
147    |
147    |
148 LL |     asm!("li x28, 0");
+    |           ^^^^^^^^^
150    |
151 note: instantiated into assembly here
151 note: instantiated into assembly here
152   --> <inline asm>:1:5
158   --> $DIR/riscv32e-registers.rs:82:11
159    |
159    |
160 LL |     asm!("li x29, 0");
+    |           ^^^^^^^^^
162    |
163 note: instantiated into assembly here
163 note: instantiated into assembly here
164   --> <inline asm>:1:5
170   --> $DIR/riscv32e-registers.rs:85:11
171    |
171    |
172 LL |     asm!("li x30, 0");
+    |           ^^^^^^^^^
174    |
175 note: instantiated into assembly here
175 note: instantiated into assembly here
176   --> <inline asm>:1:5
182   --> $DIR/riscv32e-registers.rs:88:11
183    |
183    |
184 LL |     asm!("li x31, 0");
+    |           ^^^^^^^^^
186    |
187 note: instantiated into assembly here
187 note: instantiated into assembly here
188   --> <inline asm>:1:5

The actual stderr differed from the expected stderr.
The actual stderr differed from the expected stderr.
Actual stderr saved to /checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32e/riscv32e-registers.riscv32e.stderr
To only update this specific test, also pass `--test-args abi/riscv32e-registers.rs`


error in revision `riscv32e`: 1 errors occurred comparing output.
status: exit status: 1
command: env -u RUSTC_LOG_COLOR RUSTC_ICE="0" RUST_BACKTRACE="short" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage1/bin/rustc" "/checkout/tests/ui/abi/riscv32e-registers.rs" "-Zthreads=1" "-Zsimulate-remapped-rust-src-base=/rustc/FAKE_PREFIX" "-Ztranslate-remapped-path-to-local-path=no" "-Z" "ignore-directory-in-diagnostics-source-blocks=/cargo" "-Z" "ignore-directory-in-diagnostics-source-blocks=/checkout/vendor" "--sysroot" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage1" "--cfg" "riscv32e" "--check-cfg" "cfg(FALSE,riscv32e,riscv32em,riscv32emc)" "--error-format" "json" "--json" "future-incompat" "-Ccodegen-units=1" "-Zui-testing" "-Zdeduplicate-diagnostics=no" "-Zwrite-long-types-to-disk=no" "-Cstrip=debuginfo" "-C" "prefer-dynamic" "--out-dir" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32e" "-A" "unused" "-A" "internal_features" "-Crpath" "-Cdebuginfo=0" "-Lnative=/checkout/obj/build/x86_64-unknown-linux-gnu/native/rust-test-helpers" "-L" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32e/auxiliary" "--crate-type=rlib" "--target=riscv32e-unknown-none-elf"
--- stderr -------------------------------
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:43:11
   |
   |
LL |     asm!("li x16, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x16, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:46:11
   |
LL |     asm!("li x17, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x17, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:49:11
   |
LL |     asm!("li x18, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x18, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:52:11
   |
LL |     asm!("li x19, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x19, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:55:11
   |
LL |     asm!("li x20, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x20, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:58:11
   |
LL |     asm!("li x21, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x21, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:61:11
   |
LL |     asm!("li x22, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x22, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:64:11
   |
LL |     asm!("li x23, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x23, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:67:11
   |
LL |     asm!("li x24, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x24, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:70:11
   |
LL |     asm!("li x25, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x25, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:73:11
   |
LL |     asm!("li x26, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x26, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:76:11
   |
LL |     asm!("li x27, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x27, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:79:11
   |
LL |     asm!("li x28, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x28, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:82:11
   |
LL |     asm!("li x29, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x29, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:85:11
   |
LL |     asm!("li x30, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x30, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:88:11
   |
LL |     asm!("li x31, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x31, 0
   |        ^

error: aborting due to 16 previous errors
---
diff of stderr:

2   --> $DIR/riscv32e-registers.rs:43:11
3    |
4 LL |     asm!("li x16, 0");
+    |           ^^^^^^^^^
6    |
7 note: instantiated into assembly here
7 note: instantiated into assembly here
8   --> <inline asm>:1:5
14   --> $DIR/riscv32e-registers.rs:46:11
15    |
15    |
16 LL |     asm!("li x17, 0");
+    |           ^^^^^^^^^
18    |
19 note: instantiated into assembly here
19 note: instantiated into assembly here
20   --> <inline asm>:1:5
26   --> $DIR/riscv32e-registers.rs:49:11
27    |
27    |
28 LL |     asm!("li x18, 0");
+    |           ^^^^^^^^^
30    |
31 note: instantiated into assembly here
31 note: instantiated into assembly here
32   --> <inline asm>:1:5
38   --> $DIR/riscv32e-registers.rs:52:11
39    |
39    |
40 LL |     asm!("li x19, 0");
+    |           ^^^^^^^^^
42    |
43 note: instantiated into assembly here
43 note: instantiated into assembly here
44   --> <inline asm>:1:5
50   --> $DIR/riscv32e-registers.rs:55:11
51    |
51    |
52 LL |     asm!("li x20, 0");
+    |           ^^^^^^^^^
54    |
55 note: instantiated into assembly here
55 note: instantiated into assembly here
56   --> <inline asm>:1:5
62   --> $DIR/riscv32e-registers.rs:58:11
63    |
63    |
64 LL |     asm!("li x21, 0");
+    |           ^^^^^^^^^
66    |
67 note: instantiated into assembly here
67 note: instantiated into assembly here
68   --> <inline asm>:1:5
74   --> $DIR/riscv32e-registers.rs:61:11
75    |
75    |
76 LL |     asm!("li x22, 0");
+    |           ^^^^^^^^^
78    |
79 note: instantiated into assembly here
79 note: instantiated into assembly here
80   --> <inline asm>:1:5
86   --> $DIR/riscv32e-registers.rs:64:11
87    |
87    |
88 LL |     asm!("li x23, 0");
+    |           ^^^^^^^^^
90    |
91 note: instantiated into assembly here
91 note: instantiated into assembly here
92   --> <inline asm>:1:5
98   --> $DIR/riscv32e-registers.rs:67:11
99    |
99    |
100 LL |     asm!("li x24, 0");
+    |           ^^^^^^^^^
102    |
103 note: instantiated into assembly here
103 note: instantiated into assembly here
104   --> <inline asm>:1:5
110   --> $DIR/riscv32e-registers.rs:70:11
111    |
111    |
112 LL |     asm!("li x25, 0");
+    |           ^^^^^^^^^
114    |
115 note: instantiated into assembly here
115 note: instantiated into assembly here
116   --> <inline asm>:1:5
122   --> $DIR/riscv32e-registers.rs:73:11
123    |
123    |
124 LL |     asm!("li x26, 0");
+    |           ^^^^^^^^^
126    |
127 note: instantiated into assembly here
127 note: instantiated into assembly here
128   --> <inline asm>:1:5
134   --> $DIR/riscv32e-registers.rs:76:11
135    |
135    |
136 LL |     asm!("li x27, 0");
+    |           ^^^^^^^^^
138    |
139 note: instantiated into assembly here
139 note: instantiated into assembly here
140   --> <inline asm>:1:5
146   --> $DIR/riscv32e-registers.rs:79:11
147    |
147    |
148 LL |     asm!("li x28, 0");
+    |           ^^^^^^^^^
150    |
151 note: instantiated into assembly here
151 note: instantiated into assembly here
152   --> <inline asm>:1:5
158   --> $DIR/riscv32e-registers.rs:82:11
159    |
159    |
160 LL |     asm!("li x29, 0");
+    |           ^^^^^^^^^
162    |
163 note: instantiated into assembly here
163 note: instantiated into assembly here
164   --> <inline asm>:1:5
170   --> $DIR/riscv32e-registers.rs:85:11
171    |
171    |
172 LL |     asm!("li x30, 0");
+    |           ^^^^^^^^^
174    |
175 note: instantiated into assembly here
175 note: instantiated into assembly here
176   --> <inline asm>:1:5
182   --> $DIR/riscv32e-registers.rs:88:11
183    |
183    |
184 LL |     asm!("li x31, 0");
+    |           ^^^^^^^^^
186    |
187 note: instantiated into assembly here
187 note: instantiated into assembly here
188   --> <inline asm>:1:5

The actual stderr differed from the expected stderr.
Actual stderr saved to /checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32em/riscv32e-registers.riscv32em.stderr
To update references, rerun the tests and pass the `--bless` flag
To update references, rerun the tests and pass the `--bless` flag
To only update this specific test, also pass `--test-args abi/riscv32e-registers.rs`

error in revision `riscv32em`: 1 errors occurred comparing output.
status: exit status: 1
command: env -u RUSTC_LOG_COLOR RUSTC_ICE="0" RUST_BACKTRACE="short" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage1/bin/rustc" "/checkout/tests/ui/abi/riscv32e-registers.rs" "-Zthreads=1" "-Zsimulate-remapped-rust-src-base=/rustc/FAKE_PREFIX" "-Ztranslate-remapped-path-to-local-path=no" "-Z" "ignore-directory-in-diagnostics-source-blocks=/cargo" "-Z" "ignore-directory-in-diagnostics-source-blocks=/checkout/vendor" "--sysroot" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage1" "--cfg" "riscv32em" "--check-cfg" "cfg(FALSE,riscv32e,riscv32em,riscv32emc)" "--error-format" "json" "--json" "future-incompat" "-Ccodegen-units=1" "-Zui-testing" "-Zdeduplicate-diagnostics=no" "-Zwrite-long-types-to-disk=no" "-Cstrip=debuginfo" "-C" "prefer-dynamic" "--out-dir" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32em" "-A" "unused" "-A" "internal_features" "-Crpath" "-Cdebuginfo=0" "-Lnative=/checkout/obj/build/x86_64-unknown-linux-gnu/native/rust-test-helpers" "-L" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32em/auxiliary" "--crate-type=rlib" "--target=riscv32em-unknown-none-elf"
--- stderr -------------------------------
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:43:11
   |
   |
LL |     asm!("li x16, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x16, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:46:11
   |
LL |     asm!("li x17, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x17, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:49:11
   |
LL |     asm!("li x18, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x18, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:52:11
   |
LL |     asm!("li x19, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x19, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:55:11
   |
LL |     asm!("li x20, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x20, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:58:11
   |
LL |     asm!("li x21, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x21, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:61:11
   |
LL |     asm!("li x22, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x22, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:64:11
   |
LL |     asm!("li x23, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x23, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:67:11
   |
LL |     asm!("li x24, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x24, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:70:11
   |
LL |     asm!("li x25, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x25, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:73:11
   |
LL |     asm!("li x26, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x26, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:76:11
   |
LL |     asm!("li x27, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x27, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:79:11
   |
LL |     asm!("li x28, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x28, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:82:11
   |
LL |     asm!("li x29, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x29, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:85:11
   |
LL |     asm!("li x30, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x30, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:88:11
   |
LL |     asm!("li x31, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x31, 0
   |        ^

error: aborting due to 16 previous errors
---
diff of stderr:

2   --> $DIR/riscv32e-registers.rs:43:11
3    |
4 LL |     asm!("li x16, 0");
+    |           ^^^^^^^^^
6    |
7 note: instantiated into assembly here
7 note: instantiated into assembly here
8   --> <inline asm>:1:5
14   --> $DIR/riscv32e-registers.rs:46:11
15    |
15    |
16 LL |     asm!("li x17, 0");
+    |           ^^^^^^^^^
18    |
19 note: instantiated into assembly here
19 note: instantiated into assembly here
20   --> <inline asm>:1:5
26   --> $DIR/riscv32e-registers.rs:49:11
27    |
27    |
28 LL |     asm!("li x18, 0");
+    |           ^^^^^^^^^
30    |
31 note: instantiated into assembly here
31 note: instantiated into assembly here
32   --> <inline asm>:1:5
38   --> $DIR/riscv32e-registers.rs:52:11
39    |
39    |
40 LL |     asm!("li x19, 0");
+    |           ^^^^^^^^^
42    |
43 note: instantiated into assembly here
43 note: instantiated into assembly here
44   --> <inline asm>:1:5
50   --> $DIR/riscv32e-registers.rs:55:11
51    |
51    |
52 LL |     asm!("li x20, 0");
+    |           ^^^^^^^^^
54    |
55 note: instantiated into assembly here
55 note: instantiated into assembly here
56   --> <inline asm>:1:5
62   --> $DIR/riscv32e-registers.rs:58:11
63    |
63    |
64 LL |     asm!("li x21, 0");
+    |           ^^^^^^^^^
66    |
67 note: instantiated into assembly here
67 note: instantiated into assembly here
68   --> <inline asm>:1:5
74   --> $DIR/riscv32e-registers.rs:61:11
75    |
75    |
76 LL |     asm!("li x22, 0");
+    |           ^^^^^^^^^
78    |
79 note: instantiated into assembly here
79 note: instantiated into assembly here
80   --> <inline asm>:1:5
86   --> $DIR/riscv32e-registers.rs:64:11
87    |
87    |
88 LL |     asm!("li x23, 0");
+    |           ^^^^^^^^^
90    |
91 note: instantiated into assembly here
91 note: instantiated into assembly here
92   --> <inline asm>:1:5
98   --> $DIR/riscv32e-registers.rs:67:11
99    |
99    |
100 LL |     asm!("li x24, 0");
+    |           ^^^^^^^^^
102    |
103 note: instantiated into assembly here
103 note: instantiated into assembly here
104   --> <inline asm>:1:5
110   --> $DIR/riscv32e-registers.rs:70:11
111    |
111    |
112 LL |     asm!("li x25, 0");
+    |           ^^^^^^^^^
114    |
115 note: instantiated into assembly here
115 note: instantiated into assembly here
116   --> <inline asm>:1:5
122   --> $DIR/riscv32e-registers.rs:73:11
123    |
123    |
124 LL |     asm!("li x26, 0");
+    |           ^^^^^^^^^
126    |
127 note: instantiated into assembly here
127 note: instantiated into assembly here
128   --> <inline asm>:1:5
134   --> $DIR/riscv32e-registers.rs:76:11
135    |
135    |
136 LL |     asm!("li x27, 0");
+    |           ^^^^^^^^^
138    |
139 note: instantiated into assembly here
139 note: instantiated into assembly here
140   --> <inline asm>:1:5
146   --> $DIR/riscv32e-registers.rs:79:11
147    |
147    |
148 LL |     asm!("li x28, 0");
+    |           ^^^^^^^^^
150    |
151 note: instantiated into assembly here
151 note: instantiated into assembly here
152   --> <inline asm>:1:5
158   --> $DIR/riscv32e-registers.rs:82:11
159    |
159    |
160 LL |     asm!("li x29, 0");
+    |           ^^^^^^^^^
162    |
163 note: instantiated into assembly here
163 note: instantiated into assembly here
164   --> <inline asm>:1:5
170   --> $DIR/riscv32e-registers.rs:85:11
171    |
171    |
172 LL |     asm!("li x30, 0");
+    |           ^^^^^^^^^
174    |
175 note: instantiated into assembly here
175 note: instantiated into assembly here
176   --> <inline asm>:1:5
182   --> $DIR/riscv32e-registers.rs:88:11
183    |
183    |
184 LL |     asm!("li x31, 0");
+    |           ^^^^^^^^^
186    |
187 note: instantiated into assembly here
187 note: instantiated into assembly here
188   --> <inline asm>:1:5

The actual stderr differed from the expected stderr.
The actual stderr differed from the expected stderr.
Actual stderr saved to /checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32emc/riscv32e-registers.riscv32emc.stderr
To only update this specific test, also pass `--test-args abi/riscv32e-registers.rs`


error in revision `riscv32emc`: 1 errors occurred comparing output.
status: exit status: 1
command: env -u RUSTC_LOG_COLOR RUSTC_ICE="0" RUST_BACKTRACE="short" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage1/bin/rustc" "/checkout/tests/ui/abi/riscv32e-registers.rs" "-Zthreads=1" "-Zsimulate-remapped-rust-src-base=/rustc/FAKE_PREFIX" "-Ztranslate-remapped-path-to-local-path=no" "-Z" "ignore-directory-in-diagnostics-source-blocks=/cargo" "-Z" "ignore-directory-in-diagnostics-source-blocks=/checkout/vendor" "--sysroot" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage1" "--cfg" "riscv32emc" "--check-cfg" "cfg(FALSE,riscv32e,riscv32em,riscv32emc)" "--error-format" "json" "--json" "future-incompat" "-Ccodegen-units=1" "-Zui-testing" "-Zdeduplicate-diagnostics=no" "-Zwrite-long-types-to-disk=no" "-Cstrip=debuginfo" "-C" "prefer-dynamic" "--out-dir" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32emc" "-A" "unused" "-A" "internal_features" "-Crpath" "-Cdebuginfo=0" "-Lnative=/checkout/obj/build/x86_64-unknown-linux-gnu/native/rust-test-helpers" "-L" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/abi/riscv32e-registers.riscv32emc/auxiliary" "--crate-type=rlib" "--target=riscv32emc-unknown-none-elf"
--- stderr -------------------------------
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:43:11
   |
   |
LL |     asm!("li x16, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x16, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:46:11
   |
LL |     asm!("li x17, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x17, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:49:11
   |
LL |     asm!("li x18, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x18, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:52:11
   |
LL |     asm!("li x19, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x19, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:55:11
   |
LL |     asm!("li x20, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x20, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:58:11
   |
LL |     asm!("li x21, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x21, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:61:11
   |
LL |     asm!("li x22, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x22, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:64:11
   |
LL |     asm!("li x23, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x23, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:67:11
   |
LL |     asm!("li x24, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x24, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:70:11
   |
LL |     asm!("li x25, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x25, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:73:11
   |
LL |     asm!("li x26, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x26, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:76:11
   |
LL |     asm!("li x27, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x27, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:79:11
   |
LL |     asm!("li x28, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x28, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:82:11
   |
LL |     asm!("li x29, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x29, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:85:11
   |
LL |     asm!("li x30, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x30, 0
   |        ^

error: invalid operand for instruction
error: invalid operand for instruction
##[error]  --> /checkout/tests/ui/abi/riscv32e-registers.rs:88:11
   |
LL |     asm!("li x31, 0");
   |
note: instantiated into assembly here
note: instantiated into assembly here
  --> <inline asm>:1:5
LL |     li x31, 0
   |        ^

error: aborting due to 16 previous errors

@bors
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bors commented Oct 16, 2024

💔 Test failed - checks-actions

@bors bors added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. labels Oct 16, 2024
@Urgau Urgau deleted the rollup-v431zf4 branch October 16, 2024 18:16
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