Skip to content
This repository has been archived by the owner on Apr 13, 2019. It is now read-only.

Add gdb xml register support. #160

Closed
wants to merge 44 commits into from
Closed

Add gdb xml register support. #160

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
44 commits
Select commit Hold shift + click to select a range
59a2a11
RISC-V: Update address bits to support sv39 and sv48
Mar 5, 2018
67110fb
RISC-V: Improve page table walker spec compliance
Mar 4, 2018
458d08e
RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
Apr 10, 2018
0461550
RISC-V: Simplify riscv_cpu_local_irqs_pending
Apr 19, 2018
dabcc50
RISC-V: Allow setting and clearing multiple irqs
Apr 8, 2018
970b95b
RISC-V: Move non-ops from op_helper to cpu_helper
Apr 10, 2018
e0bc582
RISC-V: Update CSR and interrupt definitions
Mar 5, 2018
0bf5716
RISC-V: Implement modular CSR helper interface
Apr 8, 2018
31aa0b4
RISC-V: Implement atomic mip/sip CSR updates
Apr 10, 2018
5fe21a8
RISC-V: Implement existential predicates for CSRs
Apr 11, 2018
3737960
RISC-V: Split out mstatus_fs from tb_flags
rth7680 Mar 28, 2018
24ece65
RISC-V: Mark mstatus.fs dirty
rth7680 Mar 28, 2018
0a656f3
RISC-V: Implement mstatus.TSR/TW/TVM
Apr 15, 2018
b379f5a
RISC-V: Add public API for the CSR dispatch table
Apr 20, 2018
c2901dd
RISC-V: Add hartid and \n to interrupt logging
Apr 22, 2018
f4399d2
RISC-V: Use riscv prefix consistently on cpu helpers
Apr 23, 2018
ad21000
RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
Apr 29, 2018
8812433
RISC-V: Add missing free for plic_hart_config
Apr 30, 2018
bea8bb0
RISC-V: Allow interrupt controllers to claim interrupts
May 6, 2018
764aa94
RISC-V: Add misa to DisasContext
May 12, 2018
fc5d882
RISC-V: Add misa.MAFD checks to translate
May 9, 2018
2ad9b10
RISC-V: Add misa runtime write support
May 9, 2018
eec015a
RISC-V: Fix CLINT timecmp low 32-bit writes
May 12, 2018
e8ae79c
RISC-V: Fix PLIC pending bitfield reads
May 12, 2018
e8b5944
RISC-V: Enable second UART on sifive_e and sifive_u
May 12, 2018
25571ed
RISC-V: Remove unnecessary disassembler constraints
May 16, 2018
fc4d86d
elf: Add RISC-V PSABI ELF header defines
May 17, 2018
34f9902
RISC-V: linux-user support for RVE ABI
kito-cheng Jun 16, 2017
9d4473b
RISC-V: Don't add NULL bootargs to device-tree
May 22, 2018
6338416
RISC-V: Support separate firmware and kernel payload
May 19, 2018
3e20277
RISC-V: Change local interrupts from edge to level
May 25, 2018
27016af
RISC-V: Add SiFive Test device to E and U series machines
Jun 19, 2018
c7b1e00
RISC-V: Add support for vectored interrupts
Jun 21, 2018
884c701
RISC-V: Convert trap debugging to trace events
Jun 21, 2018
0a13267
RISC-V: Update load reservation comment in do_interrupt
Jun 22, 2018
0b22435
sifive_prci: Read and write PRCI registers
nategraff-sifive Jul 24, 2018
d7e5d78
sifive_uart: Implement interrupt pending register
nategraff-sifive Jul 24, 2018
577f7aa
target/riscv/pmp.c: Fix PMP NAPOT decoding bug
dayeol Jul 17, 2018
cf5f50f
target/riscv/pmp.c: Fix PMP range boundary address bug
dayeol Jul 17, 2018
63801b3
riscv: remove define cpu_init()
May 15, 2018
077d5e6
hw/riscv: flatten SiFive machine bus topology
Aug 6, 2018
d621573
target/riscv: rename RISCV_FEATURE_MISA
Aug 6, 2018
79fe4f4
Merge branch 'qemu-for-upstream' into riscv-all
Aug 6, 2018
2f70fed
Add gdb xml register support.
Sep 9, 2018
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions configure
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7044,12 +7044,14 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
Expand Down
43 changes: 43 additions & 0 deletions gdb-xml/riscv-cpu.xml
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
<reg name="x0" bitsize="64"/>
<reg name="x1" bitsize="64"/>
<reg name="x2" bitsize="64"/>
<reg name="x3" bitsize="64"/>
<reg name="x4" bitsize="64"/>
<reg name="x5" bitsize="64"/>
<reg name="x6" bitsize="64"/>
<reg name="x7" bitsize="64"/>
<reg name="x8" bitsize="64"/>
<reg name="x9" bitsize="64"/>
<reg name="x10" bitsize="64"/>
<reg name="x11" bitsize="64"/>
<reg name="x12" bitsize="64"/>
<reg name="x13" bitsize="64"/>
<reg name="x14" bitsize="64"/>
<reg name="x15" bitsize="64"/>
<reg name="x16" bitsize="64"/>
<reg name="x17" bitsize="64"/>
<reg name="x18" bitsize="64"/>
<reg name="x19" bitsize="64"/>
<reg name="x20" bitsize="64"/>
<reg name="x21" bitsize="64"/>
<reg name="x22" bitsize="64"/>
<reg name="x23" bitsize="64"/>
<reg name="x24" bitsize="64"/>
<reg name="x25" bitsize="64"/>
<reg name="x26" bitsize="64"/>
<reg name="x27" bitsize="64"/>
<reg name="x28" bitsize="64"/>
<reg name="x29" bitsize="64"/>
<reg name="x30" bitsize="64"/>
<reg name="x31" bitsize="64"/>
<reg name="pc" bitsize="64"/>
</feature>
11 changes: 11 additions & 0 deletions gdb-xml/riscv-csr.xml
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.csr">
<reg name="misa" bitsize="64" regnum="0x342"/>
</feature>
43 changes: 43 additions & 0 deletions gdb-xml/riscv-fpu.xml
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.fpu">
<reg name="f0" bitsize="64"/>
<reg name="f1" bitsize="64"/>
<reg name="f2" bitsize="64"/>
<reg name="f3" bitsize="64"/>
<reg name="f4" bitsize="64"/>
<reg name="f5" bitsize="64"/>
<reg name="f6" bitsize="64"/>
<reg name="f7" bitsize="64"/>
<reg name="f8" bitsize="64"/>
<reg name="f9" bitsize="64"/>
<reg name="f10" bitsize="64"/>
<reg name="f11" bitsize="64"/>
<reg name="f12" bitsize="64"/>
<reg name="f13" bitsize="64"/>
<reg name="f14" bitsize="64"/>
<reg name="f15" bitsize="64"/>
<reg name="f16" bitsize="64"/>
<reg name="f17" bitsize="64"/>
<reg name="f18" bitsize="64"/>
<reg name="f19" bitsize="64"/>
<reg name="f20" bitsize="64"/>
<reg name="f21" bitsize="64"/>
<reg name="f22" bitsize="64"/>
<reg name="f23" bitsize="64"/>
<reg name="f24" bitsize="64"/>
<reg name="f25" bitsize="64"/>
<reg name="f26" bitsize="64"/>
<reg name="f27" bitsize="64"/>
<reg name="f28" bitsize="64"/>
<reg name="f29" bitsize="64"/>
<reg name="f30" bitsize="64"/>
<reg name="f31" bitsize="64"/>
<reg name="f32" bitsize="64"/>
</feature>
5 changes: 4 additions & 1 deletion target/riscv/cpu.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -311,6 +311,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}

riscv_cpu_register_gdb_regs_for_features(cs);

qemu_init_vcpu(cs);
cpu_reset(cs);

Expand Down Expand Up @@ -351,7 +353,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 65;
cc->gdb_num_core_regs = 33;
cc->gdb_core_xml_file = "riscv-cpu.xml";
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifdef CONFIG_USER_ONLY
Expand Down
2 changes: 2 additions & 0 deletions target/riscv/cpu.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -331,6 +331,8 @@ typedef struct {
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);

void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);

#include "exec/cpu-all.h"

#endif /* RISCV_CPU_H */
2 changes: 1 addition & 1 deletion target/riscv/csr.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ static riscv_csr_operations csr_ops[];
/* CSR function table constants */

enum {
CSR_TABLE_SIZE = 0xfff
CSR_TABLE_SIZE = 0x1000
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Good spotting. I vaguely remember this one. CSR 0xfff is out of bounds. We should roll this fragment into 0bf5716 RISC-V: Implement modular CSR helper interface When I merge the commit I can rebase and move this fragment.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

With an earlier version of the patch, I got a core dump when gdb tried to read CSR4095, because of the out-of-bounds array access.

};

/* CSR function table public API */
Expand Down
56 changes: 45 additions & 11 deletions target/riscv/gdbstub.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,13 +30,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n == 32) {
return gdb_get_regl(mem_buf, env->pc);
} else if (n < 65) {
return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
} else if (n < 4096 + 65) {
target_ulong val = 0;
if (riscv_csrrw(env, n - 65, &val, 0, 0) == 0) {
return gdb_get_regl(mem_buf, val);
}
}
return 0;
}
Expand All @@ -55,14 +48,55 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n == 32) {
env->pc = ldtul_p(mem_buf);
return sizeof(target_ulong);
} else if (n < 65) {
env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
}
return 0;
}

static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
return gdb_get_reg64(mem_buf, env->fpr[n]);
}
return 0;
}

static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
} else if (n < 4096 + 65) {
}
return 0;
}

static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 4096) {
target_ulong val = 0;
if (riscv_csrrw(env, n, &val, 0, 0) == 0) {
return gdb_get_regl(mem_buf, val);
}
}
return 0;
}

static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 4096) {
target_ulong val = ldtul_p(mem_buf);
if (riscv_csrrw(env, n - 65, NULL, val, -1) == 0) {
if (riscv_csrrw(env, n, NULL, val, -1) == 0) {
return sizeof(target_ulong);
}
}
return 0;
}

void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
/* ??? Assume all targets have FPU regs for now. */
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

We can get look at misa to see if the CPU has F or D. If D is present, F is present, so it suffices to look for F as write_misa checks these constraints. i.e.

    RISCVCPU *cpu = RISCV_CPU(cs);
    CPURISCVState *env = &cpu->env;
    if (riscv_has_ext(env, RVF)) {
        gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
                                 32, "riscv-fpu.xml", 0);
    }

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Register numbers have to match gdb, and gdb always makes the FP regs 33 to 64. I think that we will always have to register the FP regs for now, even if they aren't enabled. I will check this when I have a chance. Ideally we only register FP regs if enabled, but I suspect this will require a gdb patch, which in turn will also require a OpenOCD patch. So if we change this, we will need coordinated qemu/gdb/OpenOCD patches which will be inconvenient. It appears that this is how the ARM port works, but then they have 4 different kinds of FP registers to support, so they probably don't have a choice.

gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
32, "riscv-fpu.xml", 0);

gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-csr.xml", 0);
}