add ASR permission and target out of bounds exception priority (#128)

fix [issue ](#127)

---------

Co-authored-by: Andres Amaya Garcia <[email protected]>

src/riscv-integration.adoc

@@ -758,7 +758,7 @@ _Reserved_
 |Priority |Exc.Code |Description
 |_Highest_ |3 |Instruction address breakpoint
 | .>|*{cheri_excep_mcause}* .<|*Prior to instruction address translation:* +
-*CHERI fault*
+*CHERI fault due to PCC checks (tag, execute permission and bounds)*
 | .>|12, 1 .<|During instruction address translation: +
 First encountered page fault or access fault
 | .>|1 .<|With physical address for instruction: +
@@ -774,8 +774,13 @@ Environment call +
 Environment break +
 Load/store/AMO address breakpoint
 
-| .>|*{cheri_excep_mcause}* .<|*Prior to address translation for an explicit memory access or jump:* +
-*CHERI fault*
+| .>| *{cheri_excep_mcause}* .<| *CHERI faults due to:* +
+*PCC <<asr_perm>> clear* +
+*Branch/jump target address checks (tag, execute permissions and bounds)*
+
+| .>|*{cheri_excep_mcause}* .<|*Prior to address translation for an explicit memory access:* +
+*Load/store/AMO capability address misaligned* +
+*CHERI fault due to capability checks (tag, permissions and bounds)*
 | .>|4,6 .<|Optionally: +
 Load/store/AMO address misaligned
 | .>|13, 15, 5, 7 .<|During address translation for an explicit memory access: +
@@ -786,6 +791,8 @@ Load/store/AMO access fault
 Load/store/AMO address misaligned
 |===
 
+NOTE: the full details of the CHERI exceptions are in xref:cheri_exception_combs_descriptions[xrefstyle=short].
+
 [#medeleg,reftext="medeleg"]
 ==== Machine Trap Delegation Register (medeleg)