Tiny fixes 2 (#131)

Signed-off-by: Stefan O'Rear <[email protected]>
riscv · Feb 26, 2024 · e18679b · e18679b
1 parent 9dd9261
commit e18679b
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/src/img/menvcfgreg.edn b/src/img/menvcfgreg.edn
@@ -22,7 +22,6 @@
 (draw-box "55" {:span 16 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
-(draw-box "1" {:span 2 :borders {}})
 (draw-box "2" {:span 2 :borders {}})
 (draw-box "3" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})

diff --git a/src/riscv-legacy-integration.adoc b/src/riscv-legacy-integration.adoc
@@ -254,8 +254,9 @@ The CME bits in <<mseccfg>>, <<menvcfg>>, and <<senvcfg>> have no effect whilst
 CHERI register access is disabled.
 
 CHERI register access is disabled if XLEN in the current mode is less than
-XLENMAX or if CRE active at the current mode (<<menvcfg>>.CRE for S-mode or
-<<senvcfg>>.CRE for U-mode) is 0.
+XLENMAX, if the endianness in the current mode is not the reset value of
+<<mstatus>>.MBE, or if CRE active at the current mode (<<menvcfg>>.CRE for
+S-mode or <<senvcfg>>.CRE for U-mode) is 0.
 
 Disabling CHERI register access has no effect on implicit accesses or security
 checks.  The last capability installed in <<pcc>> and <<ddc>> before disabling