Add SiFive VCIX state register #56
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| |*Vendor* |*Name* |*Description* | ||
| |SiFive |sf.vcix_state |This dummy CSR is used to prevent the scheduler to reorder between SiFive vector instructions defined in `XSFVCP` extension. | ||
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This document should not become a registry of all vendor CSRs (or vendor instructions).
Instead, let's restrict ourselves to vendor prefixes and vendor extensions with the intent to avoid potential name collisions.
We've defined the vendor prefixes to be equal for instructions and CSRs (see the section "CSR naming scheme" above). A SiFive vendor prefix (sf.) and the XSFVCP extension are already defined above. Therefore, I think this PR is not needed.
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When I look up the As mentioned above, I don't think that |
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That's kinda special case for the vendor CSR, it's a pseudo register which used for guarantee the order between those instruction, but I agree that should not list here, otherwise other vendor will go here to add their own, and this doc will become hard to maintain. |
…6914) riscv-non-isa/riscv-toolchain-conventions#56 Resolved #106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm.
…6914) riscv-non-isa/riscv-toolchain-conventions#56 Resolved llvm/llvm-project#106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm.
…m#106914) riscv-non-isa/riscv-toolchain-conventions#56 Resolved llvm#106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm.
…m#106914) riscv-non-isa/riscv-toolchain-conventions#56 Resolved llvm#106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm.
…m#106914) riscv-non-isa/riscv-toolchain-conventions#56 Resolved llvm#106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm.
…m#106914) riscv-non-isa/riscv-toolchain-conventions#56 Resolved llvm#106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm.
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