vc4 updates for 4.5 #1421
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vc4 updates for 4.5 #1421
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Added missing CTRL and DIV clock register definitions for: PCM, SLIM, TCNT, TEC, TD0, TD1 Register information taken from: https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM which extracted the information from the header files shared by Broadcom/rpi foundation in this file: http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz Signed-off-by: Martin Sperl <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> (cherry picked from commit 2103a21)
bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control register, which may lose the other bits that are currently set by the clock dividers. It also now locks during the read/modify/write cycle of both registers. Fixes: 41691b8 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 6727f08)
Add missing locking to: * bcm2835_pll_divider_on * bcm2835_pll_divider_off to protect the read modify write cycle for the register access protecting both cm_reg and a2w_reg registers. Fixes: 41691b8 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit ec36a5c)
Current clamping of a normal divider allows a value < 1 to be valid. A divider of < 1 would actually only be possible if we had a PLL... So this patch clamps the divider to 1. Fixes: 41691b8 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 997f16b)
The current driver calculates the clock divider with fractional support enabled. But it does not enable fractional support in the control register itself resulting in an integer only divider, but in clk_set_rate responds back the fractionally divided clock frequency. This patch enables fractional support in the control register whenever there is a fractional bit set in the requested clock divider. Mash clock limits are are also handled for the PWM clock applying the correct divider limits (2 and max_int) applicable to basic fractional divider support (mash order of 1). It also adds locking to protect the read/modify/write cycle of the register modification. Fixes: 41691b8 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 959ca92)
Fix all the checkpatch complaints for clk-bcm2835.c Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 6e1e60d)
For debugging purposes under some circumstance it helps to be able to see the actual clock registers. E.g: when looking at the clock divider it is helpful to see what the actual clock divider is. This patch exposes all the clock registers specific to each clock/pll/pll-divider via debugfs. Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Acked-by: Eric Anholt <[email protected]> (cherry picked from commit 96bf9c6)
As the use of BCM2835_CLOCK_COUNT in include/dt-bindings/clock/bcm2835.h is frowned upon as it needs to get modified every time a new clock gets introduced this patch changes the clk-bcm2835 driver to use a different scheme for registration of clocks and pll, so that there is no more need for BCM2835_CLOCK_COUNT to be defined. Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 56eb3a2)
Reorganize bcm2835_clock_array so that there is no more need for separate bcm2835_*_data structures to be defined. Instead the required structures are generated inline via helper macros. To allow this to also work for pll alone it was required that the parent_pll was changed from a pointer to bcm2835_pll_data to the name of the pll instead. Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 3b15afe)
Enable the PCM clock in the SOC, which is used by the bcm2835-i2s driver. Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 33b6896)
Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 7284369)
Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E, and DSI1E. PULSE is not added because it has an extra divider. Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit d3d6f15)
In poweroff, we set the reset bit and the power down bit, but only managed to unset the reset bit for poweron. This meant that if HDMI did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the PLLH (that had been on at boot time) and never recover. Signed-off-by: Eric Anholt <[email protected]> Fixes: 41691b8 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: [email protected] Signed-off-by: Stephen Boyd <[email protected]> (cherry picked from commit d794a7b18350b7538e64248adf639f2cb8da5fb7)
Signed-off-by: Eric Anholt <[email protected]>
This will be used by the GPU driver for powering on HDMI at boot time and for 3D hang reset. Signed-off-by: Eric Anholt <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit f427fb1)
This is the pointer to the HVS device's memory where we stored the contents of *dlist. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 17eac75)
As we add actual scaling, this is going to get way more complicated. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 5c67999)
Previously, on every modeset we would allocate new display list memory, recompute changed planes, write all of them to the new memory, and pointed scanout at the new list (which will latch approximately at the next line of scanout). We let drm_atomic_helper_wait_for_vblanks() decide whether we needed to wait for a vblank after a modeset before cleaning up the old state and letting the next modeset proceed, and on legacy cursor updates we wouldn't wait. If you moved the cursor fast enough, we could potentially wrap around the display list memory area and overwrite the existing display list while it was still being scanned out, resulting in the HVS scanning out garbage or just halting. Instead of making cursor updates wait for scanout to move to the new display list area (which introduces significant cursor lag in X), we just rewrite our current display list. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 6674a90)
So far, we've only ever lit up one CRTC, so this has been fine. To extend to more displays or more planes, we need to make sure we don't run our display lists into each other. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit d8dbf44)
Previously we only did the primary and cursor plane, but overlay planes are useful and just require this setup to add, since all planes go into the HVS display list in the same way. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit fc2d6f1)
This doesn't matter yet since we only allow 1:1 scaling, but the comment clearly says we should be using the source size. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit f863e35)
This implements a simple policy for choosing scaling modes (trapezoidal for decimation, PPF for magnification), and a single PPF filter (Mitchell/Netravali's recommendation). Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 21af94c)
These were all touch-tested with modetest. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit fe4cd84)
This supports 420 and 422 subsampling with 2 or 3 planes, tested with modetest. It doesn't set up chroma subsampling position (which it appears KMS doesn't deal with yet). The LBM memory is overallocated in many cases, but apparently the docs aren't quite correct and I'll probably need to look at the hardware source to really figure it out. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit fc04023)
We'd need X to queue up an async pageflip while another is outstanding, and then take a SIGIO. I think X actually avoids sending out the next pageflip while one's already queued, but I'm not sure. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 48627eb)
If the firmware hadn't brought up HDMI for us, we need to do its power-on reset sequence (reset HD and and clear its STANDBY bits, reset HDMI, and leave the PHY disabled). Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 851479a)
This is also involved in the HDMI setup sequence so it's nice to see it. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 936f1a5)
It's used for delaying vsync in interlaced mode. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit c31806f)
It looks like when I went to add the interlaced bits, I just took the existing PV_VERT* block and indented it, instead of copy and pasting it first. Without this, changing resolution never worked. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit a7c5047)
We weren't updating the interlaced bit, so we'd scan out incorrectly if the firmware had brought up the TV encoder and we were switching to HDMI. Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit 6a60920)
The hardware provides us with separate threads for binning and rendering, and the existing model waits for them both to complete before submitting the next job. Splitting the binning and rendering submissions reduces idle time and gives us approx 20-30% speedup with some x11perf tests such as -line10 and -tilerect1. Improves openarena performance by 1.01897% +/- 0.247857% (n=16). Thanks to anholt for suggesting this. v2: Rebase on the spurious resets fix (change by anholt). Signed-off-by: Varad Gautam <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Eric Anholt <[email protected]> (cherry picked from commit ca26d28)
Fixes an error thrown every few seconds when we poll HPD when it's on a I2C to GPIO expander. Signed-off-by: Eric Anholt <[email protected]> Tested-by: Daniel Stone <[email protected]> (cherry picked from commit 0e60eab)
The original Raspberry Pi had the GPIO active high, but the later models are active low. The DT GPIO bindings allow specifying the active flag, except that it doesn't get propagated to the gpiodesc, so you have to handle it yourself. Signed-off-by: Eric Anholt <[email protected]> Tested-by: Daniel Stone <[email protected]> (cherry picked from commit 0b06e0a)
The Raspberry Pi Foundation's firmware updates are shipping device trees using the old string, so we'll keep recognizing that as this rev of V3D. Still, we should use a more specific name in the upstream DT to clarify which board is being supported, in case we do other revs of V3D in the future. Signed-off-by: Eric Anholt <[email protected]> Acked-by: Stephen Warren <[email protected]> (cherry picked from commit 90d7116)
The previous area no longer works, for reasons I haven't investigated. Just move it somewhere that works. Signed-off-by: Eric Anholt <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
We need to be able to specify different HPD pin active values in the DT based on the RPi board. Just force HDMI on for now. Signed-off-by: Eric Anholt <[email protected]>
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Here's the corresponding branch to what I sent for 4.4, but for 4.5. I saw X crash at startup at one point, but it seems to be fine now. Not sure what was up.