Disallow zero sized registers in QROMs and PRGAViaPhaseGradient

qualtran/bloqs/data_loading/qrom_base.py

@@ -281,7 +281,7 @@ def selection_registers(self) -> Tuple[Register, ...]:
         types = [
             BoundedQUInt(sb, l)
             for l, sb in zip(self.data_shape, self.selection_bitsizes)
-            if is_symbolic(l) or l > 0
+            if is_symbolic(l) or l > 1
         ]
         if len(types) == 1:
             return (Register('selection', types[0]),)

qualtran/bloqs/data_loading/select_swap_qrom_test.py

@@ -16,7 +16,7 @@
 import numpy as np
 import pytest
 
-from qualtran._infra.data_types import BoundedQUInt, QUInt
+from qualtran._infra.data_types import QUInt
 from qualtran._infra.gate_with_registers import get_named_qubits, split_qubits
 from qualtran.bloqs.data_loading import QROM
 from qualtran.bloqs.data_loading.select_swap_qrom import (
@@ -77,9 +77,7 @@ def test_select_swap_qrom(data, block_size):
         cirq.H.on_each(*dirty_target_ancilla),
     )
     all_qubits = sorted(circuit.all_qubits())
-    dtype = qrom.selection_registers[0].dtype
-    assert isinstance(dtype, BoundedQUInt)
-    for selection_integer in range(int(dtype.iteration_length)):
+    for selection_integer in range(len(data[0])):
         svals_q = QUInt(len(selection_q)).to_bits(selection_integer // qrom.block_sizes[0])
         svals_r = QUInt(len(selection_r)).to_bits(selection_integer % qrom.block_sizes[0])
         qubit_vals = {x: 0 for x in all_qubits}

qualtran/bloqs/state_preparation/state_preparation_via_rotation.py

@@ -87,8 +87,6 @@
     BloqBuilder,
     BloqDocSpec,
     GateWithRegisters,
-    QAny,
-    Register,
     Signature,
     Soquet,
     SoquetT,
@@ -248,7 +246,8 @@ def _prepare_amplitudes(self, bb: BloqBuilder, **soqs: SoquetT) -> Dict[str, Soq
             # for the normal gate loop from qubit 0 to state_bitsizes-1, if it is the adjoint
             # then the process is run backwards with the opposite turn angles
             state_qubits[qi] = bb.add(Rx(angle=np.pi / 2), q=state_qubits[qi])
-            soqs["selection"] = bb.join(state_qubits[:qi])
+            if qi:
+                soqs["selection"] = bb.join(state_qubits[:qi])
             if self.control_bitsize > 1:
                 soqs["control"] = bb.join(
                     np.array(
@@ -264,7 +263,8 @@ def _prepare_amplitudes(self, bb: BloqBuilder, **soqs: SoquetT) -> Dict[str, Soq
             if self.control_bitsize != 0:
                 soqs["prepare_control"] = bb.join(separated[:-1])
             state_qubits[qi] = separated[-1]
-            state_qubits[:qi] = bb.split(cast(Soquet, soqs.pop("selection")))
+            if qi:
+                state_qubits[:qi] = bb.split(cast(Soquet, soqs.pop("selection")))
             state_qubits[qi] = bb.add(Rx(angle=-np.pi / 2), q=state_qubits[qi])
 
         soqs["target_state"] = bb.join(state_qubits)
@@ -303,9 +303,11 @@ def _prepare_phases(self, bb: BloqBuilder, **soqs: SoquetT) -> Dict[str, SoquetT
             soqs["control"] = rot_ancilla
         ctrl_rot = self.prga_prepare_phases
         # rename some registers to make them compatible with PRGAViaPhaseGradient
-        soqs["selection"] = soqs.pop("target_state")
+        if ctrl_rot.selection_bitsize:
+            soqs["selection"] = soqs.pop("target_state")
         soqs = bb.add_d(ctrl_rot, **soqs)
-        soqs["target_state"] = soqs.pop("selection")
+        if ctrl_rot.selection_bitsize:
+            soqs["target_state"] = soqs.pop("selection")
         separated = bb.split(cast(Soquet, soqs.pop("control")))
         if self.control_bitsize != 0:
             soqs["prepare_control"] = bb.join(separated[:-1])
@@ -381,12 +383,10 @@ class PRGAViaPhaseGradient(Bloq):
 
     @property
     def signature(self) -> Signature:
-        return Signature(
-            [
-                Register("control", QAny(self.control_bitsize)),
-                Register("selection", QAny(self.selection_bitsize)),
-                Register("phase_gradient", QAny(self.phase_bitsize)),
-            ]
+        return Signature.build(
+            control=self.control_bitsize,
+            selection=self.selection_bitsize,
+            phase_gradient=self.phase_bitsize,
         )
 
     @property