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Add CircuitDag class #759
Add CircuitDag class #759
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from cirq.circuits import ( | ||
Circuit, | ||
CircuitDag, | ||
DropEmptyMoments, | ||
DropNegligible, | ||
ExpandComposite, | ||
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# Copyright 2018 The ops Developers | ||
# | ||
# Licensed under the Apache License, Version 2.0 (the "License"); | ||
# you may not use this file except in compliance with the License. | ||
# You may obtain a copy of the License at | ||
# | ||
# https://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, software | ||
# distributed under the License is distributed on an "AS IS" BASIS, | ||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
# See the License for the specific language governing permissions and | ||
# limitations under the License. | ||
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from typing import Any, Callable, Generic, Iterator, Type, TypeVar | ||
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import networkx | ||
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from cirq import ops, devices | ||
from cirq.circuits import circuit | ||
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T = TypeVar('T') | ||
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class Unique(Generic[T]): | ||
"""A wrapper for a value that doesn't compare equal to other instances. | ||
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For example: 5 == 5 but Unique(5) != Unique(5). | ||
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Unique is used by CircuitDag to wrap operations because nodes in a graph | ||
are considered the same node if they compare equal to each other. X(q0) | ||
in one moment of a Circuit and X(q0) in another moment of the Circuit are | ||
wrapped by Unique(X(q0)) so they are distinct nodes in the graph. | ||
""" | ||
def __init__(self, val: T) -> None: | ||
self.val = val | ||
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def __repr__(self): | ||
return 'Unique({}, {!r})'.format(id(self), self.val) | ||
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TSelf = TypeVar('TSelf', bound='CircuitDag') | ||
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def _default_can_reorder(op1: ops.Operation, op2: ops.Operation) -> bool: | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Call this "_disjoint_qubits" or similar so that people reading the documentation of the method using this as a default value have a description of what it does instead of how it's used. |
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"""Returns true only if the operations have qubits in common.""" | ||
return not set(op1.qubits) & set(op2.qubits) | ||
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class CircuitDag(networkx.DiGraph): | ||
"""A representation of a Circuit as a directed acyclic graph. | ||
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Nodes of the graph are instances of Unique containing each operation of a | ||
circuit. | ||
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Edges of the graph are tuples of nodes. Each edge specifies a required | ||
application order between two operations. The first must be applied before | ||
the second. | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Maybe mention whether the graph is minimalist (e.g. the transitive reduction), maximalist (transitive completion), or just somewhere arbitrary in between. |
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""" | ||
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default_can_reorder = staticmethod(_default_can_reorder) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This is a class attribute so that people can use it for themselves? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Yes. |
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def __init__(self, | ||
can_reorder: Callable[[ops.Operation, ops.Operation], bool] = | ||
_default_can_reorder, | ||
incoming_graph_data: Any = None, | ||
device: devices.Device = devices.UnconstrainedDevice | ||
) -> None: | ||
"""Initializes a CircuitDag. | ||
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Args: | ||
can_reorder: A predicate that determines if two operations may be | ||
reordered. Graph edges are created for pairs of operations | ||
where this returns False. | ||
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The default predicate allows reordering only when the operations | ||
don't share common qubits. | ||
incoming_graph_data: Data in initialize the graph. This can be any | ||
value supported by networkx.DiGraph() e.g. an edge list or | ||
another graph. | ||
device: Hardware that the circuit should be able to run on. | ||
""" | ||
super().__init__(incoming_graph_data) | ||
self.can_reorder = can_reorder | ||
self.device = device | ||
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@staticmethod | ||
def make_node(op: ops.Operation) -> Unique: | ||
return Unique(op) | ||
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@classmethod | ||
def from_circuit(cls: Type[TSelf], | ||
circuit: circuit.Circuit, | ||
can_reorder: Callable[[ops.Operation, ops.Operation], | ||
bool] = _default_can_reorder | ||
) -> TSelf: | ||
return cls.from_ops(circuit.all_operations(), | ||
can_reorder=can_reorder, | ||
device=circuit.device) | ||
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@classmethod | ||
def from_ops(cls: Type[TSelf], | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Is it necessary for these to be class methods anymore, now that there is no inheritance present? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. All done. |
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*operations: ops.OP_TREE, | ||
can_reorder: Callable[[ops.Operation, ops.Operation], bool] = | ||
_default_can_reorder, | ||
device: devices.Device = devices.UnconstrainedDevice | ||
) -> TSelf: | ||
dag = cls(can_reorder=can_reorder, device=device) | ||
for op in ops.flatten_op_tree(operations): | ||
dag.append(op) | ||
return dag | ||
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def append(self, op: ops.Operation) -> None: | ||
new_node = self.make_node(op) | ||
self.add_edges_from([(node, new_node) | ||
for node in self.nodes | ||
if not self.can_reorder(node.val, new_node.val)]) | ||
self.add_node(new_node) | ||
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def all_operations(self) -> Iterator[ops.Operation]: | ||
if not self.nodes: | ||
return | ||
g = self.copy() | ||
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def get_root_node(some_node: Unique[ops.Operation] | ||
) -> Unique[ops.Operation]: | ||
pred = g.pred | ||
while pred[some_node]: | ||
some_node = next(iter(pred[some_node])) | ||
return some_node | ||
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def get_first_node() -> Unique[ops.Operation]: | ||
return get_root_node(next(iter(g.nodes))) | ||
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def get_next_node(succ: networkx.classes.coreviews.AtlasView | ||
) -> Unique[ops.Operation]: | ||
if succ: | ||
return get_root_node(next(iter(succ))) | ||
else: | ||
return get_first_node() | ||
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node = get_first_node() | ||
while True: | ||
yield node.val | ||
succ = g.succ[node] | ||
g.remove_node(node) | ||
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if not g.nodes: | ||
return | ||
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node = get_next_node(succ) | ||
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def to_circuit(self) -> circuit.Circuit: | ||
return circuit.Circuit.from_ops( | ||
self.all_operations(), | ||
strategy=circuit.InsertStrategy.EARLIEST, | ||
device=self.device) |
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# Copyright 2018 The Cirq Developers | ||
# | ||
# Licensed under the Apache License, Version 2.0 (the "License"); | ||
# you may not use this file except in compliance with the License. | ||
# You may obtain a copy of the License at | ||
# | ||
# https://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, software | ||
# distributed under the License is distributed on an "AS IS" BASIS, | ||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
# See the License for the specific language governing permissions and | ||
# limitations under the License. | ||
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import networkx | ||
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import cirq | ||
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def test_wrapper_eq(): | ||
q0, q1 = cirq.LineQubit.range(2) | ||
eq = cirq.testing.EqualsTester() | ||
eq.add_equality_group(cirq.CircuitDag.make_node(cirq.X(q0))) | ||
eq.add_equality_group(cirq.CircuitDag.make_node(cirq.X(q0))) | ||
eq.add_equality_group(cirq.CircuitDag.make_node(cirq.Y(q0))) | ||
eq.add_equality_group(cirq.CircuitDag.make_node(cirq.X(q1))) | ||
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def test_wrapper_repr(): | ||
q0 = cirq.LineQubit(0) | ||
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node = cirq.CircuitDag.make_node(cirq.X(q0)) | ||
assert (repr(node) == | ||
'Unique(' + str(id(node)) + ', GateOperation(X, (LineQubit(0),)))') | ||
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def test_init(): | ||
dag = cirq.CircuitDag() | ||
assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert list(dag.nodes) == [] | ||
assert list(dag.edges) == [] | ||
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def test_append(): | ||
q0 = cirq.LineQubit(0) | ||
dag = cirq.CircuitDag() | ||
dag.append(cirq.X(q0)) | ||
dag.append(cirq.Y(q0)) | ||
print(dag.edges) | ||
assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert len(dag.nodes) == 2 | ||
assert ([(n1.val, n2.val) for n1, n2 in dag.edges] == | ||
[(cirq.X(q0), cirq.Y(q0))]) | ||
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def test_two_identical_ops(): | ||
q0 = cirq.LineQubit(0) | ||
dag = cirq.CircuitDag() | ||
dag.append(cirq.X(q0)) | ||
dag.append(cirq.Y(q0)) | ||
dag.append(cirq.X(q0)) | ||
assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert len(dag.nodes) == 3 | ||
assert (set((n1.val, n2.val) for n1, n2 in dag.edges) == | ||
set(((cirq.X(q0), cirq.Y(q0)), | ||
(cirq.X(q0), cirq.X(q0)), | ||
(cirq.Y(q0), cirq.X(q0))))) | ||
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def test_from_ops(): | ||
q0 = cirq.LineQubit(0) | ||
dag = cirq.CircuitDag.from_ops( | ||
cirq.X(q0), | ||
cirq.Y(q0)) | ||
assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert len(dag.nodes) == 2 | ||
assert ([(n1.val, n2.val) for n1, n2 in dag.edges] == | ||
[(cirq.X(q0), cirq.Y(q0))]) | ||
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def test_from_circuit(): | ||
q0 = cirq.LineQubit(0) | ||
circuit = cirq.Circuit.from_ops( | ||
cirq.X(q0), | ||
cirq.Y(q0)) | ||
dag = cirq.CircuitDag.from_circuit(circuit) | ||
assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert len(dag.nodes) == 2 | ||
assert ([(n1.val, n2.val) for n1, n2 in dag.edges] == | ||
[(cirq.X(q0), cirq.Y(q0))]) | ||
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def test_from_circuit_with_device(): | ||
q0 = cirq.GridQubit(5, 5) | ||
circuit = cirq.Circuit.from_ops( | ||
cirq.X(q0), | ||
cirq.Y(q0), | ||
device=cirq.google.Bristlecone) | ||
dag = cirq.CircuitDag.from_circuit(circuit) | ||
assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert dag.device == circuit.device | ||
assert len(dag.nodes) == 2 | ||
assert ([(n1.val, n2.val) for n1, n2 in dag.edges] == | ||
[(cirq.X(q0), cirq.Y(q0))]) | ||
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def test_to_empty_circuit(): | ||
circuit = cirq.Circuit() | ||
dag = cirq.CircuitDag.from_circuit(circuit) | ||
assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert circuit == dag.to_circuit() | ||
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def test_to_circuit(): | ||
q0 = cirq.LineQubit(0) | ||
circuit = cirq.Circuit.from_ops( | ||
cirq.X(q0), | ||
cirq.Y(q0)) | ||
dag = cirq.CircuitDag.from_circuit(circuit) | ||
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assert networkx.dag.is_directed_acyclic_graph(dag) | ||
# Only one possible output circuit for this simple case | ||
assert circuit == dag.to_circuit() | ||
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cirq.testing.assert_allclose_up_to_global_phase( | ||
circuit.to_unitary_matrix(), | ||
dag.to_circuit().to_unitary_matrix(), | ||
atol=1e-7) | ||
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def test_larger_circuit(): | ||
q0, q1, q2, q3 = cirq.google.Bristlecone.col(5)[:4] | ||
# This circuit does not have CZ gates on adjacent qubits because the order | ||
# dag.to_circuit() would append them is non-deterministic. | ||
circuit = cirq.Circuit.from_ops( | ||
cirq.X(q0), | ||
cirq.CZ(q1, q2), | ||
cirq.CZ(q0, q1), | ||
cirq.Y(q0), | ||
cirq.Z(q0), | ||
cirq.CZ(q1, q2), | ||
cirq.X(q0), | ||
cirq.Y(q0), | ||
cirq.CZ(q0, q1), | ||
cirq.T(q3), | ||
strategy=cirq.InsertStrategy.EARLIEST, | ||
device=cirq.google.Bristlecone) | ||
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dag = cirq.CircuitDag.from_circuit(circuit) | ||
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assert networkx.dag.is_directed_acyclic_graph(dag) | ||
assert circuit.device == dag.to_circuit().device | ||
# Operation order within a moment is non-deterministic | ||
# but text diagrams still look the same. | ||
assert (circuit.to_text_diagram() == | ||
dag.to_circuit().to_text_diagram() == | ||
""" | ||
(0, 5): ───X───@───Y───Z───X───Y───@─── | ||
│ │ | ||
(1, 5): ───@───@───@───────────────@─── | ||
│ │ | ||
(2, 5): ───@───────@─────────────────── | ||
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(3, 5): ───T─────────────────────────── | ||
""".strip()) | ||
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cirq.testing.assert_allclose_up_to_global_phase( | ||
circuit.to_unitary_matrix(), | ||
dag.to_circuit().to_unitary_matrix(), | ||
atol=1e-7) |
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google-api-python-client~=1.6 | ||
matplotlib~=2.1 | ||
networkx~=2.1 | ||
numpy~=1.13 | ||
protobuf~=3.5 | ||
sortedcontainers~=1.5 | ||
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google-api-python-client~=1.6 | ||
matplotlib~=2.2 | ||
networkx~=2.1 | ||
numpy~=1.14 | ||
protobuf~=3.5 | ||
requests~=2.18 | ||
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Add a docstring explaining why this is needed.
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Done.