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After !77

This PR replaces legacy `RI5CY` with `CV32E40P` in either the SoC (FC controller) and the cluster (8 core instances)

**HW (RTL)**:

- [x] Replace cv32e40p with OBI adapter into SoC
- [x] Add FPU wrapper into SoC using APU connection. FPU is now instantiated in `fc_subsystem`
- [x] Replace cv32e40p with OBI adapter into Cluster
- [x] Add `pulp_clock_gating` tech cell for ASIC, disable clock gating for FPGA (as in RI5CY) **[TODO: do it properly without using `ifdef`]** (#85)
- [x] Add one [performance counters test](https://github.com/pulp-platform/regression_tests/tree/cv32perf_counters/perf_counters) in assembly for cv32 to be executed with pulp-runtime

**SW**:

Main SW changes concerns:

1. Different mapping of the HW loops (`Xpulp` extensions)
2. Different structure and mapping of the performance counters
3. Enable clint timer irq (Freertos and RTL)

- [x] Change `PULP RISCV GCC toolchain` version used in the CI with cv32e40p target with: `/usr/pack/riscv-1.0-kgf/pulp-gcc-2.2.0`
- [x] Update `pulp-runtime` with cv32e40p target with: `v0.0.9`
- [x] Update `FreeRTOS` version with cv32e40p target with: `570b2c1c`

**MISC**

- [x] Update README
- [x] Update CHANGELOG

- The testset has been previously overhauled in !63 and !65. In particular !63 removed some tests that used the legacy pulp-sdk and RI5CY and were not a fit anymore with cv32

Within this project boundary, there exits three issues tracked in #87, #86 and #85 that will be addressed in separate MRs

Fixes #59 #60 #84
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bluewww committed Jul 26, 2021
2 parents 456844a + 324e5ba commit e7f5421
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60 changes: 60 additions & 0 deletions rtl/components/obi_pulp_adapter.sv
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// Copyright 2020 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.

// Author: Matteo Perotti, [email protected]
// Description: Module to adapt CV32E40P to the PULP memory system.
// It blocks multiple outstanding requests to the memory until the first one is served.

module obi_pulp_adapter (
input logic rst_ni,
input logic clk_i,
// Master (core) interface
input logic core_req_i,
// Slave (memory) interface
input logic mem_gnt_i,
input logic mem_rvalid_i,
output logic mem_req_o
);

// CU states
typedef enum logic {WAIT_GNT, WAIT_VALID} state_t;
state_t ps, ns;

// FSM next-state sequential process
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
ps <= WAIT_GNT;
end else begin
ps <= ns;
end
end

// Block multiple requests, as the memory does not support them
// core_req_i is kept stable by cv32e40p (OBI compliant)
always_comb begin
case (ps)
WAIT_GNT: begin
// Idle state, the memory has not received any request yet
mem_req_o = core_req_i;
ns = (core_req_i && mem_gnt_i) ? WAIT_VALID : WAIT_GNT;
end
WAIT_VALID: begin
// The memory has received and granted a request. Filter the next request until the memory is ready to accept it.
mem_req_o = (core_req_i && mem_rvalid_i) ? 1'b1 : 1'b0;
ns = (mem_rvalid_i && !mem_gnt_i) ? WAIT_GNT : WAIT_VALID;
end
default: begin
mem_req_o = core_req_i;
ns = WAIT_GNT;
end
endcase
end

endmodule
115 changes: 115 additions & 0 deletions rtl/fc/cv32e40p_fp_wrapper.sv
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.

// Wrapper for a fpnew
// Contributor: Davide Schiavone <[email protected]>

module cv32e40p_fp_wrapper import cv32e40p_apu_core_pkg::*;
(
// Clock and Reset
input logic clk_i,
input logic rst_ni,

// APU Side: Master port
input logic apu_req_i,
output logic apu_gnt_o,

// request channel
input logic [APU_NARGS_CPU-1:0][31:0] apu_operands_i,
input logic [APU_WOP_CPU-1:0] apu_op_i,
input logic [APU_NDSFLAGS_CPU-1:0] apu_flags_i,

// response channel
output logic apu_rvalid_o,
output logic [31:0] apu_rdata_o,
output logic [APU_NUSFLAGS_CPU-1:0] apu_rflags_o
);


import cv32e40p_pkg::*;
import fpnew_pkg::*;

logic [fpnew_pkg::OP_BITS-1:0] fpu_op;
logic fpu_op_mod;
logic fpu_vec_op;

logic [fpnew_pkg::FP_FORMAT_BITS-1:0] fpu_dst_fmt;
logic [fpnew_pkg::FP_FORMAT_BITS-1:0] fpu_src_fmt;
logic [fpnew_pkg::INT_FORMAT_BITS-1:0] fpu_int_fmt;
logic [C_RM-1:0] fp_rnd_mode;



// assign apu_rID_o = '0;
assign {fpu_vec_op, fpu_op_mod, fpu_op} = apu_op_i;

assign {fpu_int_fmt, fpu_src_fmt, fpu_dst_fmt, fp_rnd_mode} = apu_flags_i;



// -----------
// FPU Config
// -----------
// Features (enabled formats, vectors etc.)
localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
Width: C_FLEN,
EnableVectors: C_XFVEC,
EnableNanBox: 1'b0,
FpFmtMask: {C_RVF, C_RVD, C_XF16, C_XF8, C_XF16ALT},
IntFmtMask: {C_XFVEC && C_XF8, C_XFVEC && (C_XF16 || C_XF16ALT), 1'b1, 1'b0}
};

// Implementation (number of registers etc)
localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
PipeRegs: '{// FP32, FP64, FP16, FP8, FP16alt
'{C_LAT_FP32, C_LAT_FP64, C_LAT_FP16, C_LAT_FP8, C_LAT_FP16ALT}, // ADDMUL
'{default: C_LAT_DIVSQRT}, // DIVSQRT
'{default: C_LAT_NONCOMP}, // NONCOMP
'{default: C_LAT_CONV}}, // CONV
UnitTypes: '{'{default: fpnew_pkg::MERGED}, // ADDMUL
'{default: fpnew_pkg::MERGED}, // DIVSQRT
'{default: fpnew_pkg::PARALLEL}, // NONCOMP
'{default: fpnew_pkg::MERGED}}, // CONV
PipeConfig: fpnew_pkg::AFTER
};

//---------------
// FPU instance
//---------------

fpnew_top #(
.Features ( FPU_FEATURES ),
.Implementation ( FPU_IMPLEMENTATION ),
.TagType ( logic )
) i_fpnew_bulk (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.operands_i ( apu_operands_i ),
.rnd_mode_i ( fpnew_pkg::roundmode_e'(fp_rnd_mode) ),
.op_i ( fpnew_pkg::operation_e'(fpu_op) ),
.op_mod_i ( fpu_op_mod ),
.src_fmt_i ( fpnew_pkg::fp_format_e'(fpu_src_fmt) ),
.dst_fmt_i ( fpnew_pkg::fp_format_e'(fpu_dst_fmt) ),
.int_fmt_i ( fpnew_pkg::int_format_e'(fpu_int_fmt) ),
.vectorial_op_i ( fpu_vec_op ),
.tag_i ( 1'b0 ),
.in_valid_i ( apu_req_i ),
.in_ready_o ( apu_gnt_o ),
.flush_i ( 1'b0 ),
.result_o ( apu_rdata_o ),
.status_o ( apu_rflags_o ),
.tag_o ( /* unused */ ),
.out_valid_o ( apu_rvalid_o ),
.out_ready_i ( 1'b1 ),
.busy_o ( /* unused */ )
);

endmodule // cv32e40p_fp_wrapper

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