Add verilator split_var comments #367
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (4)
src/rr_arb_tree.sv|134 col 101| Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
src/rr_arb_tree.sv|136 col 101| Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
src/rr_arb_tree.sv|137 col 101| Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]
src/id_queue.sv|124 col 101| Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 134 in src/rr_arb_tree.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/rr_arb_tree.sv#L134
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"./src/rr_arb_tree.sv" range:{start:{line:134 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 136 in src/rr_arb_tree.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/rr_arb_tree.sv#L136
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./src/rr_arb_tree.sv" range:{start:{line:136 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 137 in src/rr_arb_tree.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/rr_arb_tree.sv#L137
Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]" location:{path:"./src/rr_arb_tree.sv" range:{start:{line:137 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 124 in src/id_queue.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/id_queue.sv#L124
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./src/id_queue.sv" range:{start:{line:124 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}