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Add verilator split_var comments
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Moritz Scherer committed Nov 18, 2024
1 parent c27bce3 commit 7522cba
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Showing 2 changed files with 7 additions and 7 deletions.
6 changes: 3 additions & 3 deletions src/id_queue.sv
Original file line number Diff line number Diff line change
Expand Up @@ -115,13 +115,13 @@ module id_queue #(
no_out_id_match;

logic [HtCapacity-1:0] head_tail_free,
idx_matches_in_id,
idx_matches_in_id /*verilator split_var*/,
idx_matches_out_id;

logic [CAPACITY-1:0] exists_match,
linked_data_free;

id_t match_in_id, match_out_id;
id_t match_in_id /*verilator split_var*/, match_out_id /*verilator split_var*/;

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[verible-verilog-lint] src/id_queue.sv#L124

Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./src/id_queue.sv" range:{start:{line:124 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

ht_idx_t head_tail_free_idx,
match_in_idx,
Expand Down Expand Up @@ -358,7 +358,7 @@ module id_queue #(

// Exists Lookup
for (genvar i = 0; i < CAPACITY; i++) begin: gen_lookup
data_t exists_match_bits;
data_t exists_match_bits /*verilator split_var*/;
for (genvar j = 0; j < $bits(data_t); j++) begin: gen_mask
always_comb begin
if (linked_data_q[i].free) begin
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8 changes: 4 additions & 4 deletions src/rr_arb_tree.sv
Original file line number Diff line number Diff line change
Expand Up @@ -131,10 +131,10 @@ module rr_arb_tree #(
localparam int unsigned NumLevels = unsigned'($clog2(NumIn));

/* verilator lint_off UNOPTFLAT */
idx_t [2**NumLevels-2:0] index_nodes; // used to propagate the indices
DataType [2**NumLevels-2:0] data_nodes; // used to propagate the data
logic [2**NumLevels-2:0] gnt_nodes; // used to propagate the grant to masters
logic [2**NumLevels-2:0] req_nodes; // used to propagate the requests to slave
idx_t [2**NumLevels-2:0] index_nodes /*verilator split_var*/; // used to propagate the indices

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[verible-verilog-lint] src/rr_arb_tree.sv#L134

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"./src/rr_arb_tree.sv" range:{start:{line:134 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
DataType [2**NumLevels-2:0] data_nodes /*verilator split_var*/; // used to propagate the data
logic [2**NumLevels-2:0] gnt_nodes /*verilator split_var*/; // used to propagate the grant to masters

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[verible-verilog-lint] src/rr_arb_tree.sv#L136

Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./src/rr_arb_tree.sv" range:{start:{line:136 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
logic [2**NumLevels-2:0] req_nodes /*verilator split_var*/; // used to propagate the requests to slave

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[verible-verilog-lint] src/rr_arb_tree.sv#L137

Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]" location:{path:"./src/rr_arb_tree.sv" range:{start:{line:137 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
/* lint_off */
idx_t rr_q;
logic [NumIn-1:0] req_d;
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