Skip to content

Avoid wide signals in sensitivity lists of immediate assertions #252

Avoid wide signals in sensitivity lists of immediate assertions

Avoid wide signals in sensitivity lists of immediate assertions #252

Status Success
Total duration 51s
Artifacts 1

lint.yml

on: pull_request
Verilog Sources
40s
Verilog Sources
Fit to window
Zoom out
Zoom in

Annotations

1 warning
Verilog Sources
The following actions use a deprecated Node.js version and will be forced to run on node20: actions/checkout@v3. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/

Artifacts

Produced during runtime
Name Size
verible-linter
164 Bytes