lint

Allow reset connection in SCM if FPGA target is exported. #101

	# Copyright 2024 ETH Zurich and University of Bologna.
	# Solderpad Hardware License, Version 0.51, see LICENSE for details.
	# SPDX-License-Identifier: SHL-0.51

	# Author: Michael Rogennmoser <[email protected]>

	# Run all lint checks
	name: lint
	on: [push, pull_request, workflow_dispatch]

	jobs:

	################
	# Verible Lint #
	################
	verible-lint:
	name: Lint Verilog sources
	runs-on: ubuntu-latest
	steps:
	- uses: actions/checkout@v4
	- uses: chipsalliance/verible-linter-action@main
	with:
	paths: \|
	./src
	./test
	exclude_paths: \|
	./src/ctrl_unit/cluster_icache_ctrl_reg_top.sv
	./src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv
	github_token: ${{ secrets.GITHUB_TOKEN }}
	fail_on_error: true
	reviewdog_reporter: github-check

	################
	# Lint License #
	################

	lint-license:
	runs-on: ubuntu-latest
	steps:
	- name: Checkout
	uses: actions/checkout@v4
	- name: Check license
	uses: pulp-platform/pulp-actions/lint-license@v2
	with:
	license: \|
	Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna\|lowRISC contributors).
	(Solderpad Hardware License, Version 0.51\|Licensed under the Apache License, Version 2.0), see LICENSE for details.
	SPDX-License-Identifier: (SHL-0.51\|Apache-2.0)

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