Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

fpga: Add Xilinx DDR, Linux boot, Linux apps, multiple clock domains #175

Merged
merged 2 commits into from
Nov 22, 2023
Merged

fpga: Add Xilinx DDR, Linux boot, Linux apps, multiple clock domains #175

merged 2 commits into from
Nov 22, 2023

Conversation

CyrilKoe
Copy link
Contributor

@CyrilKoe CyrilKoe commented Oct 2, 2023 •
edited
Loading

This PR goes with the MR !34

Modifs:

HW:

  • Add cdc_dst_axi_err when disabling islands
  • Add Xilinx DDR with NO_HYPERBUS parameter
  • Large XDC rework to allow CDC (host@50MHz, islands@20MHz) and faster implementation. Note: CDCs have been carefully constrained one by one giving large code diff
  • Modified how clock is generated (manually instanciate differential clock buffer which feeds both ddr and clk_wiz)

CI:

  • Add multiple boot jobs in CI
  • Add the ELABORATE_ONLY parameter (indentation large diff)
  • Added some artifact bash scripts (xilinx/common.mk) to not re-synthetize IPs

SW:

  • Add device tree
  • Replace bare metal memory map to use pointer offsets (TODO verify CI does not get longer)
  • Add image generation in sw.mk
  • Add Linux app compilation in sw.mk
  • Add addressability test app

Todo (in a later PR)

  • Add ID serializer in DDR wrapper based on Cheshire's

@CyrilKoe CyrilKoe requested a review from alex96295 as a code owner October 2, 2023 13:23
@CyrilKoe CyrilKoe force-pushed the fpga/linux_apps branch 8 times, most recently from b80a39b to 6409c45 Compare October 3, 2023 00:11
@CyrilKoe CyrilKoe changed the title Add DRAM, Linux apps Add Xilinx DDR, Linux boot, Linux apps, multiple clock domains Oct 3, 2023
@CyrilKoe CyrilKoe changed the title Add Xilinx DDR, Linux boot, Linux apps, multiple clock domains fpga: Add Xilinx DDR, Linux boot, Linux apps, multiple clock domains Oct 3, 2023
@CyrilKoe
Copy link
Contributor Author

CyrilKoe commented Oct 3, 2023 •
edited
Loading

Ready to be reviewed if the CI passes

@CyrilKoe CyrilKoe force-pushed the fpga/linux_apps branch 2 times, most recently from 54d08d9 to baba258 Compare October 3, 2023 07:18
@CyrilKoe
Copy link
Contributor Author

CyrilKoe commented Oct 3, 2023

elab-xilinx-base passed, 100% ready for review

@CyrilKoe CyrilKoe force-pushed the fpga/linux_apps branch 7 times, most recently from 2ff70b1 to 9d39a4b Compare October 3, 2023 10:55
@CyrilKoe
Copy link
Contributor Author

CyrilKoe commented Oct 3, 2023

Changing CI scripts at the moment based on MR review. But the PR content is still 100% ready to review

@CyrilKoe CyrilKoe force-pushed the fpga/linux_apps branch 7 times, most recently from edcccd3 to 0de51ba Compare October 9, 2023 15:46
@CyrilKoe CyrilKoe force-pushed the fpga/linux_apps branch 2 times, most recently from ec28302 to 7c80998 Compare October 10, 2023 08:34
@CyrilKoe
Copy link
Contributor Author

@alex96295 PR ready

alex96295
alex96295 reviewed Oct 14, 2023
View reviewed changes
carfield.mk Outdated Show resolved Hide resolved
@alex96295 alex96295 mentioned this pull request Oct 15, 2023
Closed
@CyrilKoe CyrilKoe force-pushed the fpga/linux_apps branch 3 times, most recently from ee7d282 to eef7dfa Compare October 16, 2023 05:05
@CyrilKoe
Copy link
Contributor Author

@alex96295 rebased on latest master (Oct 19), PR ready

alex96295
alex96295 reviewed Nov 21, 2023
View reviewed changes
carfield.mk Outdated Show resolved Hide resolved
alex96295
alex96295 reviewed Nov 21, 2023
View reviewed changes
target/xilinx/src/dram_wrapper_xilinx.sv Outdated
// Instianciate data width resizer //
/////////////////////////////////////

if (cfg.DataWidth != SoC_DataWidth) begin : gen_dw_converter
Copy link
Collaborator

@alex96295 alex96295 Nov 21, 2023 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The dw converter module already handles all the cases between the slv data width and the mst data width, so it is redundant in this case

alex96295
alex96295 reviewed Nov 21, 2023
View reviewed changes
target/xilinx/src/dram_wrapper_xilinx.sv Outdated
// ID resizer //
/////////////////

if (cfg.IdWidth != SoC_IdWidth) begin : gen_iw_converter
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

DITTO for the iw converter

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks

@CyrilKoe
fpga: Add Xilinx DDR, Linux boot, Linux apps, multiple clock domains
8c705be 
fpga: Add device tree and boot ci job

fpga: Add flash utility and corrected soc_clk

fpga: Setup soc_clk@50MHz and alt_clk@20MHz

fpga: Major sdc rework

fpga: Adding handmade artifacts scripts for Xilinx ips

fpga: Added spatz cdc constraints and removed tracer target from pulp_cluster

fpga: Added integer cdc constraints

fpga: Added slv err for integer, safety and spatz

linux: adding first linux app tests
@alex96295
Copy link
Collaborator

@CyrilKoe I had a look, I think the PR is OK. Maybe we are missing some more verbose README in the xilinx folder, that we will anyway improve in #237 for the whole platform as in Cheshire

If you are fine, I will merge once CI succeeds

@alex96295
Copy link
Collaborator

Merging, thanks for the great work!

@alex96295 alex96295 merged commit 078c493 into main Nov 22, 2023
7 checks passed
@alex96295 alex96295 deleted the fpga/linux_apps branch November 22, 2023 09:17
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@alex96295 alex96295 alex96295 left review comments

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@CyrilKoe @alex96295