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fpga: DDR and SPI
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fpga: Add device tree and boot ci job

fpga: Add flash utility and corrected soc_clk

fpga: soc_clk@50MHz and alt_clk@20MHz

fpga: Major sdc rework

fpga: Adding handmade artifacts scripts for Xilinx ips

fpga: Added spatz cdc constraints and removed tracer target from pulp_cluster

fpga: Added integer cdc constraints

fpga: added slv err for integer, safety and spatz

linux: adding first linux app tests
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@CyrilKoe
CyrilKoe committed Oct 3, 2023
1 parent d4c10d7 commit 54d08d9
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Showing 37 changed files with 1,871 additions and 1,153 deletions.
1 change: 1 addition & 0 deletions Bender.yml
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Expand Up @@ -72,6 +72,7 @@ sources:
files:
- target/xilinx/src/carfield_top_xilinx.sv
- target/xilinx/src/dram_wrapper.sv
- target/xilinx/src/cdc_dst_axi_err.sv
- target/xilinx/src/overrides/tc_clk_xilinx.sv

- target: intel16_elab_only
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1 change: 1 addition & 0 deletions bender-xilinx.mk
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Expand Up @@ -21,5 +21,6 @@ $(eval $(call check_enable_island,GEN_PULP_CLUSTER))
$(eval $(call check_enable_island,GEN_SAFETY_ISLAND))
$(eval $(call check_enable_island,GEN_SPATZ_CLUSTER))
$(eval $(call check_enable_island,GEN_OPEN_TITAN))
$(eval $(call check_enable_island,NO_HYPERBUS))

# note : bender targets are later modified in xilinx.mk
2 changes: 1 addition & 1 deletion carfield.mk
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Expand Up @@ -100,7 +100,7 @@ endif
######################

CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
CAR_NONFREE_COMMIT ?= 56a40e56f60b6a1e1ead1373c273d51bbb5c9c4f
CAR_NONFREE_COMMIT ?= cbabc86ab678ccf6ad60c2651d1f1bbbe3897f66

## Clone the non-free verification IP for the Carfield TB
car-nonfree-init:
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160 changes: 154 additions & 6 deletions hw/carfield.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,14 @@ module carfield
parameter islands_cfg_t IslandsCfg = carfield_pkg::IslandsCfgDefault,
parameter int unsigned HypNumPhys = 2,
parameter int unsigned HypNumChips = 2,
`ifdef NO_HYPERBUS // bender-xilinx.mk
parameter int unsigned LlcIdWidth,
parameter int unsigned LlcArWidth,
parameter int unsigned LlcAwWidth,
parameter int unsigned LlcBWidth,
parameter int unsigned LlcRWidth,
parameter int unsigned LlcWWidth,
`endif
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic
) (
Expand Down Expand Up @@ -122,6 +130,7 @@ module carfield
output logic [SlinkNumChan-1:0] slink_rcv_clk_o,
input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i,
output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o,
`ifndef NO_HYPERBUS // bender-xilinx.mk
// HyperBus interface
output logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
output logic [HypNumPhys-1:0] hyper_ck_o,
Expand All @@ -133,6 +142,25 @@ module carfield
output logic [HypNumPhys-1:0][7:0] hyper_dq_o,
output logic [HypNumPhys-1:0] hyper_dq_oe_o,
output logic [HypNumPhys-1:0] hyper_reset_no,
`else
// LLC interface
output logic [LlcArWidth-1:0] llc_ar_data,
output logic [ LogDepth:0] llc_ar_wptr,
input logic [ LogDepth:0] llc_ar_rptr,
output logic [LlcAwWidth-1:0] llc_aw_data,
output logic [ LogDepth:0] llc_aw_wptr,
input logic [ LogDepth:0] llc_aw_rptr,
input logic [ LlcBWidth-1:0] llc_b_data,
input logic [ LogDepth:0] llc_b_wptr,
output logic [ LogDepth:0] llc_b_rptr,
input logic [ LlcRWidth-1:0] llc_r_data,
input logic [ LogDepth:0] llc_r_wptr,
output logic [ LogDepth:0] llc_r_rptr,
output logic [ LlcWWidth-1:0] llc_w_data,
output logic [ LogDepth:0] llc_w_wptr,
input logic [ LogDepth:0] llc_w_rptr,
`endif // NO_HYPERBUS

// External reg interface slaves (async)
// Currently for PLL and Padframe
output logic [1:0] ext_reg_async_slv_req_o,
Expand Down Expand Up @@ -401,6 +429,7 @@ localparam int unsigned IntClusterAxiMstRWidth =
carfield_reg_req_t [iomsb(NumSyncRegSlv):0] ext_reg_req;
carfield_reg_rsp_t [iomsb(NumSyncRegSlv):0] ext_reg_rsp;

`ifndef NO_HYPERBUS // bender-xilinx.mk
localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth +
$clog2(AxiIn.num_in)+
Cfg.LlcNotBypass ;
Expand All @@ -423,12 +452,6 @@ localparam int unsigned LlcWWidth = (2**LogDepth)*
axi_pkg::w_width(Cfg.AxiDataWidth,
Cfg.AxiUserWidth );

logic hyper_isolate_req, hyper_isolated_rsp;
logic security_island_isolate_req;

logic [iomsb(Cfg.AxiExtNumSlv-1):0] slave_isolate_req, slave_isolated_rsp, slave_isolated;
logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp;

logic [LlcArWidth-1:0] llc_ar_data;
logic [ LogDepth:0] llc_ar_wptr;
logic [ LogDepth:0] llc_ar_rptr;
Expand All @@ -445,6 +468,14 @@ logic [ LlcWWidth-1:0] llc_w_data;
logic [ LogDepth:0] llc_w_wptr;
logic [ LogDepth:0] llc_w_rptr;

`endif // NO_HYPERBUS

logic hyper_isolate_req, hyper_isolated_rsp;
logic security_island_isolate_req;

logic [iomsb(Cfg.AxiExtNumSlv-1):0] slave_isolate_req, slave_isolated_rsp, slave_isolated;
logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp;

// All AXI Slaves (except the Integer Cluster and the Mailbox)
logic [iomsb(Cfg.AxiExtNumSlv-2):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_aw_wptr;
Expand Down Expand Up @@ -1084,6 +1115,7 @@ cheshire i_cheshire_wrap (
.vga_blue_o ( )
);

`ifndef NO_HYPERBUS // bender-xilinx.mk
// Hyperbus
hyperbus_wrap #(
.NumChips ( HypNumChips ),
Expand Down Expand Up @@ -1155,6 +1187,7 @@ hyperbus_wrap #(
.hyper_dq_oe_o,
.hyper_reset_no
);
`endif // NO_HYPERBUS

// Reconfigurable L2 Memory
// Host Clock Domain
Expand Down Expand Up @@ -1368,6 +1401,42 @@ safety_island_synth_wrapper #(
end
else begin : gen_no_safety_island
assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i;
cdc_dst_axi_err #(
.AxiInIdWidth ( AxiSlvIdWidth ),
.LogDepth ( LogDepth ),
.CdcSyncStages ( SyncStages ),
.axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ),
.axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ),
.axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ),
.axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ),
.axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ),
.axi_in_resp_t ( carfield_axi_slv_rsp_t ),
.axi_in_req_t ( carfield_axi_slv_req_t ),
.AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ),
.AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ),
.AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ),
.AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ),
.AsyncAxiInRWidth ( CarfieldAxiSlvRWidth )
) i_safety_island_axi_err (
.clk_i ( safety_clk ),
.rst_ni ( safety_rst_n ),
.pwr_on_rst_ni ( safety_pwr_on_rst_n ),
.async_axi_in_aw_data_i ( axi_slv_ext_aw_data [SafetyIslandSlvIdx] ),
.async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [SafetyIslandSlvIdx] ),
.async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [SafetyIslandSlvIdx] ),
.async_axi_in_ar_data_i ( axi_slv_ext_ar_data [SafetyIslandSlvIdx] ),
.async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [SafetyIslandSlvIdx] ),
.async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [SafetyIslandSlvIdx] ),
.async_axi_in_w_data_i ( axi_slv_ext_w_data [SafetyIslandSlvIdx] ),
.async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [SafetyIslandSlvIdx] ),
.async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [SafetyIslandSlvIdx] ),
.async_axi_in_r_data_o ( axi_slv_ext_r_data [SafetyIslandSlvIdx] ),
.async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [SafetyIslandSlvIdx] ),
.async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [SafetyIslandSlvIdx] ),
.async_axi_in_b_data_o ( axi_slv_ext_b_data [SafetyIslandSlvIdx] ),
.async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [SafetyIslandSlvIdx] ),
.async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [SafetyIslandSlvIdx] )
);
end

// PULP integer cluster
Expand Down Expand Up @@ -1484,6 +1553,47 @@ int_cluster i_integer_cluster (
.async_data_master_b_rptr_o ( axi_mst_intcluster_b_rptr )
);
end
else begin : gen_no_pulp_cluster
cdc_dst_axi_err #(
.AxiInIdWidth ( IntClusterAxiIdInWidth ),
.LogDepth ( LogDepth ),
.CdcSyncStages ( SyncStages ),
.axi_in_aw_chan_t ( axi_intcluster_slv_aw_chan_t ),
.axi_in_w_chan_t ( axi_intcluster_slv_w_chan_t ),
.axi_in_b_chan_t ( axi_intcluster_slv_b_chan_t ),
.axi_in_ar_chan_t ( axi_intcluster_slv_ar_chan_t ),
.axi_in_r_chan_t ( axi_intcluster_slv_r_chan_t ),
.axi_in_resp_t ( axi_intcluster_slv_rsp_t ),
.axi_in_req_t ( axi_intcluster_slv_req_t ),
.AsyncAxiInAwWidth ( (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth,IntClusterAxiIdInWidth,
Cfg.AxiUserWidth)),
.AsyncAxiInWWidth ( (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth,Cfg.AxiUserWidth) ),
.AsyncAxiInBWidth ( (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdInWidth,Cfg.AxiUserWidth) ),
.AsyncAxiInArWidth ( (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,IntClusterAxiIdInWidth,
Cfg.AxiUserWidth)),
.AsyncAxiInRWidth ( (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth,IntClusterAxiIdInWidth,
Cfg.AxiUserWidth))
) i_pulp_cluster_axi_err (
.clk_i ( pulp_clk ),
.rst_ni ( pulp_rst_n ),
.pwr_on_rst_ni ( pulp_pwr_on_rst_n ),
.async_axi_in_aw_data_i ( axi_slv_intcluster_aw_data ),
.async_axi_in_aw_wptr_i ( axi_slv_intcluster_aw_wptr ),
.async_axi_in_aw_rptr_o ( axi_slv_intcluster_aw_rptr ),
.async_axi_in_ar_data_i ( axi_slv_intcluster_ar_data ),
.async_axi_in_ar_wptr_i ( axi_slv_intcluster_ar_wptr ),
.async_axi_in_ar_rptr_o ( axi_slv_intcluster_ar_rptr ),
.async_axi_in_w_data_i ( axi_slv_intcluster_w_data ),
.async_axi_in_w_wptr_i ( axi_slv_intcluster_w_wptr ),
.async_axi_in_w_rptr_o ( axi_slv_intcluster_w_rptr ),
.async_axi_in_r_data_o ( axi_slv_intcluster_r_data ),
.async_axi_in_r_wptr_o ( axi_slv_intcluster_r_wptr ),
.async_axi_in_r_rptr_i ( axi_slv_intcluster_r_rptr ),
.async_axi_in_b_data_o ( axi_slv_intcluster_b_data ),
.async_axi_in_b_wptr_o ( axi_slv_intcluster_b_wptr ),
.async_axi_in_b_rptr_i ( axi_slv_intcluster_b_rptr )
);
end

// Floating Point Spatz Cluster

Expand Down Expand Up @@ -1584,6 +1694,44 @@ if (IslandsCfg.EnSpatzCluster) begin : gen_spatz_cluster
.cluster_probe_o ( car_regs_hw2reg.spatz_cluster_busy.d )
);
end
else begin : gen_no_spatz_cluster
cdc_dst_axi_err #(
.AxiInIdWidth ( AxiSlvIdWidth ),
.LogDepth ( LogDepth ),
.CdcSyncStages ( SyncStages ),
.axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ),
.axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ),
.axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ),
.axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ),
.axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ),
.axi_in_resp_t ( carfield_axi_slv_rsp_t ),
.axi_in_req_t ( carfield_axi_slv_req_t ),
.AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ),
.AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ),
.AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ),
.AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ),
.AsyncAxiInRWidth ( CarfieldAxiSlvRWidth )
) i_spatz_cluster_axi_err (
.clk_i ( spatz_clk ),
.rst_ni ( spatz_rst_n ),
.pwr_on_rst_ni ( spatz_pwr_on_rst_n ),
.async_axi_in_aw_data_i ( axi_slv_ext_aw_data [FPClusterSlvIdx] ),
.async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [FPClusterSlvIdx] ),
.async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [FPClusterSlvIdx] ),
.async_axi_in_ar_data_i ( axi_slv_ext_ar_data [FPClusterSlvIdx] ),
.async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [FPClusterSlvIdx] ),
.async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [FPClusterSlvIdx] ),
.async_axi_in_w_data_i ( axi_slv_ext_w_data [FPClusterSlvIdx] ),
.async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [FPClusterSlvIdx] ),
.async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [FPClusterSlvIdx] ),
.async_axi_in_r_data_o ( axi_slv_ext_r_data [FPClusterSlvIdx] ),
.async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [FPClusterSlvIdx] ),
.async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [FPClusterSlvIdx] ),
.async_axi_in_b_data_o ( axi_slv_ext_b_data [FPClusterSlvIdx] ),
.async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [FPClusterSlvIdx] ),
.async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [FPClusterSlvIdx] )
);
end

// Security Island
logic secd_mbox_intr;
Expand Down
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