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[HW] Optimize addrgen for OS-on operation #383

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merged 4 commits into from
Jan 14, 2025
Merged

[HW] Optimize addrgen for OS-on operation #383

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40a42a1
[hardware] Cut MMU-enable path
mp-17 Jan 6, 2025
935f625
[hardware] Optimize addrgen timing for OS-on operation
mp-17 Jan 6, 2025
7db0e46
[hardware] Enable OS by default
mp-17 Jan 6, 2025
eda709a
[CHANGELOG] Update Changelog
mp-17 Jan 6, 2025
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2 changes: 2 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -86,6 +86,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Pre-calculate timing-critical addresses before addrgen stage
- Update all GitHub Actions for CI
- Update READMEs with FPGA implementation instructions
- Optimize `addrgen` timing for OS-on operation
- Enable OS by default

## 3.0.0 - 2023-09-08

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15 changes: 11 additions & 4 deletions hardware/src/ara.sv
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Expand Up @@ -10,7 +10,7 @@ module ara import ara_pkg::*; #(
// RVV Parameters
parameter int unsigned NrLanes = 0, // Number of parallel vector lanes.
parameter int unsigned VLEN = 0, // VLEN [bit]
parameter int unsigned OSSupport = 0,
parameter int unsigned OSSupport = 1,
// Support for floating-point data types
parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble,
// External support for vfrec7, vfrsqrt7
Expand Down Expand Up @@ -52,6 +52,7 @@ module ara import ara_pkg::*; #(
input axi_resp_t axi_resp_i
);

`include "common_cells/registers.svh"
`include "ara/ara_typedef.svh"
import cf_math_pkg::idx_width;

Expand Down Expand Up @@ -433,22 +434,24 @@ module ara import ara_pkg::*; #(
logic vstu_mask_ready;

// Optional OS support
logic acc_mmu_misaligned_ex, acc_mmu_req, acc_mmu_is_store, acc_mmu_dtlb_hit, acc_mmu_valid, acc_mmu_en;
logic acc_mmu_misaligned_ex, acc_mmu_req, acc_mmu_is_store, acc_mmu_dtlb_hit, acc_mmu_valid;
logic acc_mmu_en, acc_mmu_en_q;
logic [riscv::VLEN-1:0] acc_mmu_vaddr;
logic [riscv::PLEN-1:0] acc_mmu_paddr;
logic [riscv::PPNW-1:0] acc_mmu_dtlb_ppn;
ariane_pkg::exception_t acc_mmu_exception;

if (OSSupport) begin
assign acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex = acc_mmu_misaligned_ex;
assign acc_resp_o.acc_mmu_req.acc_mmu_req = acc_mmu_req;
assign acc_resp_o.acc_mmu_req.acc_mmu_vaddr = acc_mmu_vaddr;
assign acc_resp_o.acc_mmu_req.acc_mmu_is_store = acc_mmu_is_store;
assign acc_mmu_en = acc_req_i.acc_mmu_en;
assign acc_mmu_dtlb_hit = acc_req_i.acc_mmu_resp.acc_mmu_dtlb_hit;
assign acc_mmu_dtlb_ppn = acc_req_i.acc_mmu_resp.acc_mmu_dtlb_ppn;
assign acc_mmu_valid = acc_req_i.acc_mmu_resp.acc_mmu_valid;
assign acc_mmu_paddr = acc_req_i.acc_mmu_resp.acc_mmu_paddr;
assign acc_mmu_exception = acc_req_i.acc_mmu_resp.acc_mmu_exception;
assign acc_mmu_en = acc_req_i.acc_mmu_en;
end else begin
assign acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex = '0;
assign acc_resp_o.acc_mmu_req.acc_mmu_req = '0;
Expand All @@ -462,6 +465,10 @@ module ara import ara_pkg::*; #(
assign acc_mmu_exception = '0;
end

// Break path for acc_mmu_en. This signal can afford some additional latency
// since vector mem ops take multiple cycles to reach the addrgen
`FF(acc_mmu_en_q, acc_mmu_en, '0, clk_i, rst_ni);

vlsu #(
.NrLanes (NrLanes ),
.VLEN (VLEN ),
Expand Down Expand Up @@ -515,7 +522,7 @@ module ara import ara_pkg::*; #(
.addrgen_operand_valid_i (sldu_addrgen_operand_valid ),
.addrgen_operand_ready_o (addrgen_operand_ready ),
// CSR input
.en_ld_st_translation_i (acc_req_i.acc_mmu_en ),
.en_ld_st_translation_i (acc_mmu_en_q ),
// Interface with CVA6's sv39 MMU
.mmu_misaligned_ex_o (acc_mmu_misaligned_ex ),
.mmu_req_o (acc_mmu_req ),
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2 changes: 1 addition & 1 deletion hardware/src/ara_soc.sv
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Expand Up @@ -10,7 +10,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
// RVV Parameters
parameter int unsigned NrLanes = 0, // Number of parallel vector lanes.
parameter int unsigned VLEN = 0, // VLEN [bit]
parameter int unsigned OSSupport = 0, // Support for OS
parameter int unsigned OSSupport = 1, // Support for OS
// Support for floating-point data types
parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble,
// External support for vfrec7, vfrsqrt7
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2 changes: 1 addition & 1 deletion hardware/src/ara_system.sv
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Expand Up @@ -10,7 +10,7 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
// RVV Parameters
parameter int unsigned NrLanes = 0, // Number of parallel vector lanes.
parameter int unsigned VLEN = 0, // VLEN [bit]
parameter int unsigned OSSupport = 0, // Support for floating-point data types
parameter int unsigned OSSupport = 1, // Support for floating-point data types
parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble,
// External support for vfrec7, vfrsqrt7
parameter fpext_support_e FPExtSupport = FPExtSupportEnable,
Expand Down
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