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Update debug.rst #675

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Dec 3, 2021
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Update debug.rst #675

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Update debug.rst
davideschiavone Nov 10, 2021
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feedback PR 675
davideschiavone Nov 10, 2021
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12 changes: 12 additions & 0 deletions docs/source/debug.rst
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Expand Up @@ -178,3 +178,15 @@ Execuitng the EBREAK instruction when the core is in Debug Mode shall result in

- The core remains in Debug Mode and execution jumps back to the beginning of the debug code located at ``dm_halt_addr_i``
- none of the CSRs are modified


.. _interrupts_single-stepping:

Interrupts during Single-Step Behavior
--------------------------------------

The CV32E40P CPU is compliant with the 0.13.2 RISC-V Debug spec.
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I think this is a bit too strong. I would say that the 40P is not compliant to the intended interpretation of the 0.13.2 specification, but that this intended behavior was only clarified in version 1.0.0.

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agree and fixed

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let's wait for @strichmo before merging in

The RISC-V Debug spec specified what the behavior of interrupts occurring during Single-Step must be only in version 1.0.0, after the implementation of the CV32E40P core.
See https://github.com/riscv/riscv-debug-spec/issues/510.
The CV32E40P executes the first instruction of the interrupt handler and retires it before re-entering in Debug Mode, which is prohibited in version 1.0.0 but not specified in 0.13.2. For details about the specific use-case, please refer to https://github.com/openhwgroup/core-v-verif/issues/904.