Update debug.rst #675
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Update debug.rst #675
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docs/source/debug.rst
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| Interrupts during Single-Step Behavior | ||
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| The CV32E40P CPU is compliant with the 0.13.2 RISC-V Debug spec. |
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I think this is a bit too strong. I would say that the 40P is not compliant to the intended interpretation of the 0.13.2 specification, but that this intended behavior was only clarified in version 1.0.0.
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agree and fixed
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let's wait for @strichmo before merging in
Silabs-ArjanB
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Nov 10, 2021
pascalgouedo
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This should clarify interrupts during single-step to fix #669