Document immediate sign-extend for PULP post-increment loads/stores #616
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Component:Doc
For issues in the Documentation (e.g. for README.md files)
PARAM:PULP_XPULP
Issue depends on the PULP_XPULP parameter
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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davideschiavone
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zarubaf
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Update code from upstream repository https://github.com/openhwgroup/cv32e40p.git to revision 842bf0676f50589b84eea5fe2954eaf71b03a669 * Create CITATION.cff (openhwgroup/cv32e40p#667) (Pasquale Davide Schiavone) * update README with correct link to documentation (openhwgroup/cv32e40p#666) (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#657 (openhwgroup/cv32e40p#658) (Pasquale Davide Schiavone) * deleted redundant mul custom instructions (openhwgroup/cv32e40p#661) (Pasquale Davide Schiavone) * stricter decoder to fix openhwgroup/cv32e40p#650 (openhwgroup/cv32e40p#659) (Pasquale Davide Schiavone) * update format in instruction set extensions file (Pasquale Davide Schiavone) * Delete core_versions.rst2 (Pasquale Davide Schiavone) * remove pmp unused file (openhwgroup/cv32e40p#643) (Pasquale Davide Schiavone) * make USE_ISS a run-time switch instead of compile-time should still be compatible with older versions of core-v-verif testbench (Steve Richmond) * changing RTL to be compliant with verible (openhwgroup/cv32e40p#638) (Pasquale Davide Schiavone) * Updated with new (backward compatible) version and new location of OBI spec (Arjan Bink) * removed ignore inputs from lec script (Pasquale Davide Schiavone) * fixed openhwgroup/cv32e40p#616 (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#605 (Pasquale Davide Schiavone) * look for positive pass in LEC script (Pasquale Davide Schiavone) * improved README and lec script (Pasquale Davide Schiavone) * added script for LEC openhwgroup/cv32e40p#607 (davideschiavone) Signed-off-by: Florian Zaruba <[email protected]>
gmartin102
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Sep 28, 2021
* Remove cv32e40p patch * Update openhwgroup_cv32e40p to openhwgroup/cv32e40p@842bf06 Update code from upstream repository https://github.com/openhwgroup/cv32e40p.git to revision 842bf0676f50589b84eea5fe2954eaf71b03a669 * Create CITATION.cff (openhwgroup/cv32e40p#667) (Pasquale Davide Schiavone) * update README with correct link to documentation (openhwgroup/cv32e40p#666) (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#657 (openhwgroup/cv32e40p#658) (Pasquale Davide Schiavone) * deleted redundant mul custom instructions (openhwgroup/cv32e40p#661) (Pasquale Davide Schiavone) * stricter decoder to fix openhwgroup/cv32e40p#650 (openhwgroup/cv32e40p#659) (Pasquale Davide Schiavone) * update format in instruction set extensions file (Pasquale Davide Schiavone) * Delete core_versions.rst2 (Pasquale Davide Schiavone) * remove pmp unused file (openhwgroup/cv32e40p#643) (Pasquale Davide Schiavone) * make USE_ISS a run-time switch instead of compile-time should still be compatible with older versions of core-v-verif testbench (Steve Richmond) * changing RTL to be compliant with verible (openhwgroup/cv32e40p#638) (Pasquale Davide Schiavone) * Updated with new (backward compatible) version and new location of OBI spec (Arjan Bink) * removed ignore inputs from lec script (Pasquale Davide Schiavone) * fixed openhwgroup/cv32e40p#616 (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#605 (Pasquale Davide Schiavone) * look for positive pass in LEC script (Pasquale Davide Schiavone) * improved README and lec script (Pasquale Davide Schiavone) * added script for LEC openhwgroup/cv32e40p#607 (davideschiavone) Signed-off-by: Florian Zaruba <[email protected]> * vendor/cv32e40p: Re-vendor
gmartin102
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Oct 4, 2021
* Adding A2 Boot code directory Signed-off-by: Greg Martin <[email protected]> * Updated A2 boot files for I2C slave boot Signed-off-by: Greg Martin <[email protected]> * Update sized of bootrom to use input parameter for size Signed-off-by: Greg Martin <[email protected]> * Fixed linker script for bootrom Signed-off-by: Greg Martin <[email protected]> * Verilator fusesoc cleanup and Watchdog timer corretctions, added Host i2c slave boot to bootrom Signed-off-by: Greg Martin <[email protected]> * Added fileset for simulation ram to eliminate defines in rtl Signed-off-by: Greg Martin <[email protected]> * Fixed typo in mem_init section of core file Signed-off-by: Greg Martin <[email protected]> * corrected missing inversion on simulation ram byte enables Signed-off-by: Greg Martin <[email protected]> * Fixed fusesoc core file for linting of new simulation ram file Signed-off-by: Greg Martin <[email protected]> * Fixes for Bootloader and various simulator fixes for verilator and QuestaSim (#173) * Adding A2 Boot code directory Signed-off-by: Greg Martin <[email protected]> * Updated A2 boot files for I2C slave boot Signed-off-by: Greg Martin <[email protected]> * Update sized of bootrom to use input parameter for size Signed-off-by: Greg Martin <[email protected]> * Fixed linker script for bootrom Signed-off-by: Greg Martin <[email protected]> * Verilator fusesoc cleanup and Watchdog timer corretctions, added Host i2c slave boot to bootrom Signed-off-by: Greg Martin <[email protected]> * Added fileset for simulation ram to eliminate defines in rtl Signed-off-by: Greg Martin <[email protected]> * Fixed typo in mem_init section of core file Signed-off-by: Greg Martin <[email protected]> * corrected missing inversion on simulation ram byte enables Signed-off-by: Greg Martin <[email protected]> * Fixed fusesoc core file for linting of new simulation ram file Signed-off-by: Greg Martin <[email protected]> * sprillity sram module for math blocks for simulation/emulation to support synthesis Signed-off-by: Greg Martin <[email protected]> * Update efpga Source files for simulation/emulation/syntehsis Signed-off-by: Greg Martin <[email protected]> * Added STM for efpga test modes and refactored clocking to be consistant across simulation/emulation and synthesis targets Signed-off-by: Greg Martin <[email protected]> * fixed STM signal name Signed-off-by: Greg Martin <[email protected]> * IOscript fixes for synthesis top level file Signed-off-by: Greg Martin <[email protected]> * Additional changes for fusesoc support of various targets Signed-off-by: Greg Martin <[email protected]> * Fixed STM pulldown for emulation Signed-off-by: Greg Martin <[email protected]> * Added gitignore for a2_boot Signed-off-by: Greg Martin <[email protected]> * Updated mem files Signed-off-by: Greg Martin <[email protected]> * Updated boot.mem files Signed-off-by: Greg Martin <[email protected]> * Testbench fixes Signed-off-by: Greg Martin <[email protected]> * moved DW02_mac to exmulation only Signed-off-by: Greg Martin <[email protected]> * separated bw multipler for synth and sim from emulation inferred multiplier Signed-off-by: Greg Martin <[email protected]> * stm_i output enable Signed-off-by: Greg Martin <[email protected]> * Upgrade/cv32 (#174) * Remove cv32e40p patch * Update openhwgroup_cv32e40p to openhwgroup/cv32e40p@842bf06 Update code from upstream repository https://github.com/openhwgroup/cv32e40p.git to revision 842bf0676f50589b84eea5fe2954eaf71b03a669 * Create CITATION.cff (openhwgroup/cv32e40p#667) (Pasquale Davide Schiavone) * update README with correct link to documentation (openhwgroup/cv32e40p#666) (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#657 (openhwgroup/cv32e40p#658) (Pasquale Davide Schiavone) * deleted redundant mul custom instructions (openhwgroup/cv32e40p#661) (Pasquale Davide Schiavone) * stricter decoder to fix openhwgroup/cv32e40p#650 (openhwgroup/cv32e40p#659) (Pasquale Davide Schiavone) * update format in instruction set extensions file (Pasquale Davide Schiavone) * Delete core_versions.rst2 (Pasquale Davide Schiavone) * remove pmp unused file (openhwgroup/cv32e40p#643) (Pasquale Davide Schiavone) * make USE_ISS a run-time switch instead of compile-time should still be compatible with older versions of core-v-verif testbench (Steve Richmond) * changing RTL to be compliant with verible (openhwgroup/cv32e40p#638) (Pasquale Davide Schiavone) * Updated with new (backward compatible) version and new location of OBI spec (Arjan Bink) * removed ignore inputs from lec script (Pasquale Davide Schiavone) * fixed openhwgroup/cv32e40p#616 (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#605 (Pasquale Davide Schiavone) * look for positive pass in LEC script (Pasquale Davide Schiavone) * improved README and lec script (Pasquale Davide Schiavone) * added script for LEC openhwgroup/cv32e40p#607 (davideschiavone) Signed-off-by: Florian Zaruba <[email protected]> * vendor/cv32e40p: Re-vendor * deleted A2_boot directory -- correct boot code is in a2_boot Signed-off-by: Greg Martin <[email protected]> * Added Copyright notices Signed-off-by: Greg Martin <[email protected]> Co-authored-by: Florian Zaruba <[email protected]>
MikeOpenHWGroup
added a commit
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Sep 9, 2022
* Adding A2 Boot code directory Signed-off-by: Greg Martin <[email protected]> * Updated A2 boot files for I2C slave boot Signed-off-by: Greg Martin <[email protected]> * Update sized of bootrom to use input parameter for size Signed-off-by: Greg Martin <[email protected]> * Fixed linker script for bootrom Signed-off-by: Greg Martin <[email protected]> * Verilator fusesoc cleanup and Watchdog timer corretctions, added Host i2c slave boot to bootrom Signed-off-by: Greg Martin <[email protected]> * Added fileset for simulation ram to eliminate defines in rtl Signed-off-by: Greg Martin <[email protected]> * Fixed typo in mem_init section of core file Signed-off-by: Greg Martin <[email protected]> * corrected missing inversion on simulation ram byte enables Signed-off-by: Greg Martin <[email protected]> * Fixed fusesoc core file for linting of new simulation ram file Signed-off-by: Greg Martin <[email protected]> * Fixes for Bootloader and various simulator fixes for verilator and QuestaSim (#173) * Adding A2 Boot code directory Signed-off-by: Greg Martin <[email protected]> * Updated A2 boot files for I2C slave boot Signed-off-by: Greg Martin <[email protected]> * Update sized of bootrom to use input parameter for size Signed-off-by: Greg Martin <[email protected]> * Fixed linker script for bootrom Signed-off-by: Greg Martin <[email protected]> * Verilator fusesoc cleanup and Watchdog timer corretctions, added Host i2c slave boot to bootrom Signed-off-by: Greg Martin <[email protected]> * Added fileset for simulation ram to eliminate defines in rtl Signed-off-by: Greg Martin <[email protected]> * Fixed typo in mem_init section of core file Signed-off-by: Greg Martin <[email protected]> * corrected missing inversion on simulation ram byte enables Signed-off-by: Greg Martin <[email protected]> * Fixed fusesoc core file for linting of new simulation ram file Signed-off-by: Greg Martin <[email protected]> * sprillity sram module for math blocks for simulation/emulation to support synthesis Signed-off-by: Greg Martin <[email protected]> * Update efpga Source files for simulation/emulation/syntehsis Signed-off-by: Greg Martin <[email protected]> * Added STM for efpga test modes and refactored clocking to be consistant across simulation/emulation and synthesis targets Signed-off-by: Greg Martin <[email protected]> * fixed STM signal name Signed-off-by: Greg Martin <[email protected]> * IOscript fixes for synthesis top level file Signed-off-by: Greg Martin <[email protected]> * Additional changes for fusesoc support of various targets Signed-off-by: Greg Martin <[email protected]> * Fixed STM pulldown for emulation Signed-off-by: Greg Martin <[email protected]> * Added gitignore for a2_boot Signed-off-by: Greg Martin <[email protected]> * Updated mem files Signed-off-by: Greg Martin <[email protected]> * Updated boot.mem files Signed-off-by: Greg Martin <[email protected]> * Testbench fixes Signed-off-by: Greg Martin <[email protected]> * moved DW02_mac to exmulation only Signed-off-by: Greg Martin <[email protected]> * separated bw multipler for synth and sim from emulation inferred multiplier Signed-off-by: Greg Martin <[email protected]> * stm_i output enable Signed-off-by: Greg Martin <[email protected]> * Upgrade/cv32 (#174) * Remove cv32e40p patch * Update openhwgroup_cv32e40p to openhwgroup/cv32e40p@842bf06 Update code from upstream repository https://github.com/openhwgroup/cv32e40p.git to revision 842bf0676f50589b84eea5fe2954eaf71b03a669 * Create CITATION.cff (openhwgroup/cv32e40p#667) (Pasquale Davide Schiavone) * update README with correct link to documentation (openhwgroup/cv32e40p#666) (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#657 (openhwgroup/cv32e40p#658) (Pasquale Davide Schiavone) * deleted redundant mul custom instructions (openhwgroup/cv32e40p#661) (Pasquale Davide Schiavone) * stricter decoder to fix openhwgroup/cv32e40p#650 (openhwgroup/cv32e40p#659) (Pasquale Davide Schiavone) * update format in instruction set extensions file (Pasquale Davide Schiavone) * Delete core_versions.rst2 (Pasquale Davide Schiavone) * remove pmp unused file (openhwgroup/cv32e40p#643) (Pasquale Davide Schiavone) * make USE_ISS a run-time switch instead of compile-time should still be compatible with older versions of core-v-verif testbench (Steve Richmond) * changing RTL to be compliant with verible (openhwgroup/cv32e40p#638) (Pasquale Davide Schiavone) * Updated with new (backward compatible) version and new location of OBI spec (Arjan Bink) * removed ignore inputs from lec script (Pasquale Davide Schiavone) * fixed openhwgroup/cv32e40p#616 (Pasquale Davide Schiavone) * fix openhwgroup/cv32e40p#605 (Pasquale Davide Schiavone) * look for positive pass in LEC script (Pasquale Davide Schiavone) * improved README and lec script (Pasquale Davide Schiavone) * added script for LEC openhwgroup/cv32e40p#607 (davideschiavone) Signed-off-by: Florian Zaruba <[email protected]> * vendor/cv32e40p: Re-vendor * deleted A2_boot directory -- correct boot code is in a2_boot Signed-off-by: Greg Martin <[email protected]> * Clean-up for Synthesis Signed-off-by: Greg Martin <[email protected]> * Format fixes Signed-off-by: Greg Martin <[email protected]> * Add support for Vivado xsim (#186) Signed-off-by: Mike Thompson <[email protected]> * ci: Fix Python version (#192) * ci: Fix Python Version for dev branch (#193) * Add support for Vivado xsim Signed-off-by: Mike Thompson <[email protected]> * ci: Fix Python Version for dev branch Signed-off-by: Mike Thompson <[email protected]> * Restore vendor contributions (delete `ifdef XSIM...) Signed-off-by: Mike Thompson <[email protected]> * Restore XSIM changes Signed-off-by: Mike Thompson <[email protected]> * memory map for core-v-mcu (#195) * Create CITATION.cff * added memory map in doc Signed-off-by: Davide Schiavone <[email protected]> * Dev (#191) * Fixed GPIO15, 30,31 from testio errors Signed-off-by: Greg Martin <[email protected]> * Updated files for synthesis Signed-off-by: Greg Martin <[email protected]> * Update simulation mem init files Signed-off-by: Greg Martin <[email protected]> * synthesis changes Signed-off-by: Greg Martin <[email protected]> * Added SDIO peripheral and fixed pinout for sdio pmod Signed-off-by: Greg Martin <[email protected]> * Added SDIO peripheral and fixed pinout for sdio pmod Signed-off-by: Greg Martin <[email protected]> * UDMA fixes for no efpga Signed-off-by: Greg Martin <[email protected]> * Added SDIO peripheral Signed-off-by: Greg Martin <[email protected]> * systhesis changes Signed-off-by: Greg Martin <[email protected]> * Added SDIO udma to SoC Signed-off-by: Greg Martin <[email protected]> * changed pulp_soc_defines to svh suffix Signed-off-by: Greg Martin <[email protected]> * removal of XPULP parameter and PR comments incorporated Signed-off-by: Greg Martin <[email protected]> * Corrected cv32e40p Parameters and boot compiler options Signed-off-by: Greg Martin <[email protected]> * Fixed dm_exception address and sdio block write timeout Signed-off-by: Greg Martin <[email protected]> * Fix documentation of the CORE-V MCU memory map. (#196) Files changed: * docs/doc-src/mmap.rst: Fix RST table syntax, provide hyperlinks to referenced files in GitHub, add link to PULP debug unit documentation. Signed-off-by: Jeremy Bennett <[email protected]> * Fixed mem_init files for simulation (#202) Signed-off-by: Greg Martin <[email protected]> * Dev (#205) * Removed cluster logic and fixed multiple drivers, added PLL control for new PLL Signed-off-by: Greg Martin <[email protected]> * Cleaned up formating for ci Signed-off-by: Greg Martin <[email protected]> * Dev 1 (#208) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <[email protected]> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <[email protected]> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <[email protected]> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <[email protected]> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <[email protected]> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <[email protected]> * Removal of Floating point unit Signed-off-by: Greg Martin <[email protected]> * Fixed FLL address decode problem Signed-off-by: Greg Martin <[email protected]> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <[email protected]> * removed vendor specific model Signed-off-by: Greg Martin <[email protected]> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <[email protected]> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <[email protected]> * removed stale file Signed-off-by: Greg Martin <[email protected]> * Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <[email protected]> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <[email protected]> * Vendor `axi` Co-authored-by: Someshwar M S <[email protected]> Co-authored-by: Florian Zaruba <[email protected]> * Updated `dev` branch (#209) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <[email protected]> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <[email protected]> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <[email protected]> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <[email protected]> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <[email protected]> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <[email protected]> * Removal of Floating point unit Signed-off-by: Greg Martin <[email protected]> * Fixed FLL address decode problem Signed-off-by: Greg Martin <[email protected]> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <[email protected]> * removed vendor specific model Signed-off-by: Greg Martin <[email protected]> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <[email protected]> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <[email protected]> * removed stale file Signed-off-by: Greg Martin <[email protected]> * Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <[email protected]> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <[email protected]> * Vendor `axi` Co-authored-by: Greg Martin <[email protected]> Co-authored-by: Someshwar M S <[email protected]> * Added support for building emulation on Genesys2 FPGA board Signed-off-by: Greg Martin <[email protected]> * Dev (#210) * Dev 1 (#208) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <[email protected]> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <[email protected]> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <[email protected]> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <[email protected]> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <[email protected]> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <[email protected]> * Removal of Floating point unit Signed-off-by: Greg Martin <[email protected]> * Fixed FLL address decode problem Signed-off-by: Greg Martin <[email protected]> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <[email protected]> * removed vendor specific model Signed-off-by: Greg Martin <[email protected]> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <[email protected]> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <[email protected]> * removed stale file Signed-off-by: Greg Martin <[email protected]> * Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <[email protected]> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <[email protected]> * Vendor `axi` Co-authored-by: Someshwar M S <[email protected]> Co-authored-by: Florian Zaruba <[email protected]> * Updated `dev` branch (#209) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <[email protected]> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <[email protected]> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <[email protected]> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <[email protected]> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <[email protected]> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <[email protected]> * Removal of Floating point unit Signed-off-by: Greg Martin <[email protected]> * Fixed FLL address decode problem Signed-off-by: Greg Martin <[email protected]> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <[email protected]> * removed vendor specific model Signed-off-by: Greg Martin <[email protected]> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <[email protected]> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <[email protected]> * removed stale file Signed-off-by: Greg Martin <[email protected]> * Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <[email protected]> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <[email protected]> * Vendor `axi` Co-authored-by: Greg Martin <[email protected]> Co-authored-by: Someshwar M S <[email protected]> * Update README.md Co-authored-by: Someshwar M S <[email protected]> Co-authored-by: Florian Zaruba <[email protected]> * fixed docs/Makefile for Nexys -- still needs genesys doc support Signed-off-by: Greg Martin <[email protected]> * Bootloader changes for UART srec boot Signed-off-by: Greg Martin <[email protected]> * FIx Makefile to run format after ioscript Signed-off-by: Greg Martin <[email protected]> * Addedd missing include files for bootloader Signed-off-by: Greg Martin <[email protected]> * Delete spi.h Unused file * Delete PerceptiaPLL_reg_defs.h Unused file * Fixes to Verilator clock generation and re-inclusion of verilatorBoot.mem file Signed-off-by: Greg Martin <[email protected]> * Fixes to Verilator clock generation Signed-off-by: Greg Martin <[email protected]> * Quick Start Guide Signed-off-by: Mike Thompson <[email protected]> * Add optional Make argument for Nexys bitmap Signed-off-by: Mike Thompson <[email protected]> * Point to Quick Start Guide Signed-off-by: Mike Thompson <[email protected]> * Update README.md * Create empty * Add files via upload * Delete empty * Add files via upload * Add files via upload * Delete libs directory * Delete notes.txt * Delete openocd-gdbpipe-hs2.cfg * Delete openocd-gdbpipe-olimex.cfg * Delete openocd-nexys-hs2.cfg * Delete openocd-nexys-olimex.cfg * Delete oppenocd.log * Delete run_cli * Delete serialPort.py * Delete spi_load.py * Add files via upload * Create empty * Add files via upload * Delete empty * Create empty * Add files via upload * Delete empty * Add files via upload * Add files via upload * Create empty * Add files via upload * Add files via upload * Add files via upload * Add files via upload * Delete cli_tests directory * Update README.md * Add instructions for Thumbdrive * Add image of Nexys A7 board Signed-off-by: Mike Thompson <[email protected]> * Integrate image * Update README.md * Update README.md * Respond to feedback from @DBees * Edits for clarity * check whether verible is installed (#216) Signed-off-by: Massimiliano Giacometti <[email protected]> Co-authored-by: Massimiliano Giacometti <[email protected]> * Genesys2 (#211) * Dev 1 (#208) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <[email protected]> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <[email protected]> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <[email protected]> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <[email protected]> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <[email protected]> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <[email protected]> * Removal of Floating point unit Signed-off-by: Greg Martin <[email protected]> * Fixed FLL address decode problem Signed-off-by: Greg Martin <[email protected]> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <[email protected]> * removed vendor specific model Signed-off-by: Greg Martin <[email protected]> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <[email protected]> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <[email protected]> * removed stale file Signed-off-by: Greg Martin <[email protected]> * Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <[email protected]> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <[email protected]> * Vendor `axi` Co-authored-by: Someshwar M S <[email protected]> Co-authored-by: Florian Zaruba <[email protected]> * Updated `dev` branch (#209) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <[email protected]> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <[email protected]> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <[email protected]> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <[email protected]> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <[email protected]> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <[email protected]> * Removal of Floating point unit Signed-off-by: Greg Martin <[email protected]> * Fixed FLL address decode problem Signed-off-by: Greg Martin <[email protected]> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <[email protected]> * removed vendor specific model Signed-off-by: Greg Martin <[email protected]> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <[email protected]> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <[email protected]> * removed stale file Signed-off-by: Greg Martin <[email protected]> * Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * More Lint fixes Signed-off-by: Greg Martin <[email protected]> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <[email protected]> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <[email protected]> * Vendor `axi` Co-authored-by: Greg Martin <[email protected]> Co-authored-by: Someshwar M S <[email protected]> * Added support for building emulation on Genesys2 FPGA board Signed-off-by: Greg Martin <[email protected]> * fixed docs/Makefile for Nexys -- still needs genesys doc support Signed-off-by: Greg Martin <[email protected]> * Bootloader changes for UART srec boot Signed-off-by: Greg Martin <[email protected]> * FIx Makefile to run format after ioscript Signed-off-by: Greg Martin <[email protected]> * Addedd missing include files for bootloader Signed-off-by: Greg Martin <[email protected]> * Delete spi.h Unused file * Delete PerceptiaPLL_reg_defs.h Unused file * Fixes to Verilator clock generation and re-inclusion of verilatorBoot.mem file Signed-off-by: Greg Martin <[email protected]> * Fixes to Verilator clock generation Signed-off-by: Greg Martin <[email protected]> Co-authored-by: Someshwar M S <[email protected]> Co-authored-by: Florian Zaruba <[email protected]> * Point to local QSG * Hotfix: fix links in README * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <[email protected]> * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <[email protected]> * Respond to gmartin feedback: Pseudo UART enabled by default Signed-off-by: Mike Thompson <[email protected]> * Add XSIM compile-time guard Signed-off-by: Mike Thompson <[email protected]> * hook for AWS Codebuild (#221) Signed-off-by: Massimiliano Giacometti <[email protected]> Co-authored-by: Massimiliano Giacometti <[email protected]> * Initial steps towards regressionable tests (#220) * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <[email protected]> * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <[email protected]> * Respond to gmartin feedback: Pseudo UART enabled by default Signed-off-by: Mike Thompson <[email protected]> * Add XSIM compile-time guard Signed-off-by: Mike Thompson <[email protected]> * Clarify use of JTAG port (#222) * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <[email protected]> * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <[email protected]> * Respond to gmartin feedback: Pseudo UART enabled by default Signed-off-by: Mike Thompson <[email protected]> * Add XSIM compile-time guard Signed-off-by: Mike Thompson <[email protected]> * Clarify JTAG port operation Signed-off-by: Mike Thompson <[email protected]> * README updated with Ashling Opella-LD connection details * Nexys-A7 Ashling Opella-LD connection image * updated Ashling Opella_LD connection image path * Opella-LD pin out table changes * update CORE-V-MCU Quick Start Guide for WLS2 users (#227) * update CORE-V-MCU Quick Start Guide for WLS2 users * updates for apt dependencies * added instructions for NOR flash (#234) Co-authored-by: Massimiliano Giacometti <[email protected]> * Fix vendor check (#231) Signed-off-by: Greg Martin <[email protected]> Signed-off-by: Mike Thompson <[email protected]> Signed-off-by: Davide Schiavone <[email protected]> Signed-off-by: Jeremy Bennett <[email protected]> Co-authored-by: Greg Martin <[email protected]> Co-authored-by: Greg Martin <[email protected]> Co-authored-by: Florian Zaruba <[email protected]> Co-authored-by: Mike Thompson <[email protected]> Co-authored-by: Pasquale Davide Schiavone <[email protected]> Co-authored-by: Jeremy Bennett <[email protected]> Co-authored-by: Someshwar M S <[email protected]> Co-authored-by: rickoco <[email protected]> Co-authored-by: suppamax <[email protected]> Co-authored-by: Massimiliano Giacometti <[email protected]> Co-authored-by: promodkumar-ashling <[email protected]> Co-authored-by: promodkumar-ashling <[email protected]>
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For the following instructions the documentation does not indicate that the immediate is sign-extended:
My proposal would be to replace 'rs1 += Imm[11:0]' by 'rs1 += Sext(Imm[11:0])' in their descriptions.
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