Merge pull request #2461 from dd-BeeNee/cv32e40p/dev_bnl_ww23

Add RTL Code Coverage waivers following confirmation using SLEC app of JasperGold and SiemensEDA QuestaFormal.

cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do

@@ -161,6 +161,12 @@ coverage exclude -line 1237 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv
 coverage exclude -line 1237 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. }
 coverage exclude -line 399 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No interrupt during debug mode. To waive corner case to happen during FIRST_FETCH 1 clk cycle. }
 coverage exclude -line 640 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {HWLoop1 cannot be nested in HWLoop0.}
-coverage exclude -line 675 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No case when ID not ready for single stepped instruction. }
+coverage exclude -line 632 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {When removing the lines, SLEC app of JasperGold was not able to find counter-example showing a mismach on all the output between the original and the modified file.}
+coverage exclude -line 642 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {When removing the lines, SLEC app of JasperGold was not able to find counter-example showing a mismach on all the output between the original and the modified file.}
+coverage exclude -line 675 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {When removing the lines, SLEC app of JasperGold was not able to find counter-example showing a mismach on all the output between the original and the modified file.}
+coverage exclude -line 1187 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {AllFalse condition proven as unreacheable with a specific assertion using Siemens EDA QuestaFormal.}
+coverage exclude -line 1210 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {AllFalse condition proven as unreacheable with a specific assertion using Siemens EDA QuestaFormal.}
+coverage exclude -feccondrow 1241 5 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Specific condition proven as unreacheable with a specific assertion using Siemens EDA QuestaFormal.}
+coverage exclude -feccondrow 1241 10 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw}
 coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/interrupt_assert_i -recursive -comment {this is TB module bind to RTL. No need code coverage.}
 coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/prefetch_controller_i/prefetch_controller_sva -recursive -comment {this is TB module bind to RTL. No need code coverage.}