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[sysrst_ctrl] Convert IRQ type to status
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Fixes lowRISC#21832

Signed-off-by: Michael Schaffner <[email protected]>
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@msfschaffner @a-will
msfschaffner authored and a-will committed Mar 11, 2024
1 parent fed24a6 commit 9680f67
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Showing 14 changed files with 220 additions and 117 deletions.
7 changes: 4 additions & 3 deletions hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
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Expand Up @@ -31,6 +31,7 @@
interrupt_list: [
{ name: "event_detected",
desc: "Common interrupt triggered by combo or keyboard events.",
type: "status"
}
],
alert_list: [
Expand Down Expand Up @@ -278,7 +279,7 @@
{ name: "ULP_STATUS",
desc: "Ultra low power status",
swaccess: "rw1c",
hwaccess: "hwo",
hwaccess: "hrw",
resval: "0",
tags: [ // the value of these regs is determined by the
// value on the pins, hence it cannot be predicted.
Expand Down Expand Up @@ -972,7 +973,7 @@
interrupt action is configured in the corresponding !!COM_OUT_CTL register.
''',
swaccess: "rw1c",
hwaccess: "hwo",
hwaccess: "hrw",
resval: "0",
tags: [ // the value of these regs is determined by the
// value on the pins, hence it cannot be predicted.
Expand Down Expand Up @@ -1003,7 +1004,7 @@
{ name: "KEY_INTR_STATUS",
desc: "key interrupt source",
swaccess: "rw1c",
hwaccess: "hwo",
hwaccess: "hrw",
resval: "0",
tags: [ // the value of these regs is determined by the value on the pins
// or other CSRs, hence it cannot be predicted.
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2 changes: 1 addition & 1 deletion hw/ip/sysrst_ctrl/doc/interfaces.md
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Expand Up @@ -38,7 +38,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

| Interrupt Name | Type | Description |
|:-----------------|:-------|:--------------------------------------------------------|
| event_detected | Event | Common interrupt triggered by combo or keyboard events. |
| event_detected | Status | Common interrupt triggered by combo or keyboard events. |

## Security Alerts

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4 changes: 2 additions & 2 deletions hw/ip/sysrst_ctrl/doc/registers.md
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Expand Up @@ -58,13 +58,13 @@ Interrupt State Register
### Fields

```wavejson
{"reg": [{"name": "event_detected", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
{"reg": [{"name": "event_detected", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
```

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:---------------|:--------------------------------------------------------|
| 31:1 | | | | Reserved |
| 0 | rw1c | 0x0 | event_detected | Common interrupt triggered by combo or keyboard events. |
| 0 | ro | 0x0 | event_detected | Common interrupt triggered by combo or keyboard events. |

## INTR_ENABLE
Interrupt Enable Register
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3 changes: 3 additions & 0 deletions hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
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Expand Up @@ -337,6 +337,9 @@ module sysrst_ctrl
.intr_state_i(reg2hw.intr_state),
.intr_enable_i(reg2hw.intr_enable),
.intr_test_i(reg2hw.intr_test),
.key_intr_status_i(reg2hw.key_intr_status),
.combo_intr_status_i(reg2hw.combo_intr_status),
.ulp_status_i(reg2hw.ulp_status),
.wkup_status_o(hw2reg.wkup_status),
.intr_state_o(hw2reg.intr_state),
.key_intr_status_o(hw2reg.key_intr_status),
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32 changes: 16 additions & 16 deletions hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_intr.sv
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Expand Up @@ -17,10 +17,13 @@ module sysrst_ctrl_intr
input [NumCombo-1:0] aon_combo_intr_i,
input aon_ulp_wakeup_pulse_i,

input sysrst_ctrl_reg2hw_wkup_status_reg_t wkup_status_i,
input sysrst_ctrl_reg2hw_intr_state_reg_t intr_state_i,
input sysrst_ctrl_reg2hw_intr_enable_reg_t intr_enable_i,
input sysrst_ctrl_reg2hw_intr_test_reg_t intr_test_i,
input sysrst_ctrl_reg2hw_wkup_status_reg_t wkup_status_i,
input sysrst_ctrl_reg2hw_intr_state_reg_t intr_state_i,
input sysrst_ctrl_reg2hw_intr_enable_reg_t intr_enable_i,
input sysrst_ctrl_reg2hw_intr_test_reg_t intr_test_i,
input sysrst_ctrl_reg2hw_key_intr_status_reg_t key_intr_status_i,
input sysrst_ctrl_reg2hw_combo_intr_status_reg_t combo_intr_status_i,
input sysrst_ctrl_reg2hw_ulp_status_reg_t ulp_status_i,

output sysrst_ctrl_hw2reg_wkup_status_reg_t wkup_status_o,
output sysrst_ctrl_hw2reg_intr_state_reg_t intr_state_o,
Expand Down Expand Up @@ -57,10 +60,8 @@ module sysrst_ctrl_intr
always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
if (!rst_aon_ni) begin
aon_staging_reqs_q <= '0;
end else if (aon_ld_req && |aon_reqs) begin
aon_staging_reqs_q <= aon_reqs;
end else if (aon_ld_req) begin
aon_staging_reqs_q <= '0;
aon_staging_reqs_q <= aon_reqs;
end else if (|aon_reqs) begin
aon_staging_reqs_q <= aon_staging_reqs_q | aon_reqs;
end
Expand All @@ -70,7 +71,7 @@ module sysrst_ctrl_intr
logic aon_ack;

// staging has pending requsts
assign aon_ld_req = (aon_req_hold_q == '0) & |aon_staging_reqs_q;
assign aon_ld_req = (aon_req_hold_q == '0) && |aon_staging_reqs_q;

// request hold self clears when the handshake cycle is complete
always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
Expand Down Expand Up @@ -168,21 +169,20 @@ module sysrst_ctrl_intr
assign ulp_status_o.d = 1'b1;
assign ulp_status_o.de = ulp_wakeup_pulse;

// Aggregate interrupt event pulses.
logic intr_event_pulse;
assign intr_event_pulse = |{ulp_wakeup_pulse,
combo_intr,
h2l_key_intr,
l2h_key_intr};
// Aggregate interrupt event statuses.
logic intr_event_status;
assign intr_event_status = |{ulp_status_i,
combo_intr_status_i,
key_intr_status_i};

// instantiate interrupt hardware primitive
prim_intr_hw #(
.Width(1),
.IntrT("Event")
.IntrT("Status")
) u_sysrst_ctrl_intr_o (
.clk_i,
.rst_ni,
.event_intr_i (intr_event_pulse),
.event_intr_i (intr_event_status),
.reg2hw_intr_enable_q_i (intr_enable_i.q),
.reg2hw_intr_test_q_i (intr_test_i.q),
.reg2hw_intr_test_qe_i (intr_test_i.qe),
Expand Down
113 changes: 90 additions & 23 deletions hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,10 @@ package sysrst_ctrl_reg_pkg;
logic q;
} sysrst_ctrl_reg2hw_ulp_ctl_reg_t;

typedef struct packed {
logic q;
} sysrst_ctrl_reg2hw_ulp_status_reg_t;

typedef struct packed {
logic q;
} sysrst_ctrl_reg2hw_wkup_status_reg_t;
Expand Down Expand Up @@ -344,6 +348,66 @@ package sysrst_ctrl_reg_pkg;
} bat_disable;
} sysrst_ctrl_reg2hw_com_out_ctl_mreg_t;

typedef struct packed {
struct packed {
logic q;
} combo3_h2l;
struct packed {
logic q;
} combo2_h2l;
struct packed {
logic q;
} combo1_h2l;
struct packed {
logic q;
} combo0_h2l;
} sysrst_ctrl_reg2hw_combo_intr_status_reg_t;

typedef struct packed {
struct packed {
logic q;
} flash_wp_l_l2h;
struct packed {
logic q;
} ec_rst_l_l2h;
struct packed {
logic q;
} ac_present_l2h;
struct packed {
logic q;
} key2_in_l2h;
struct packed {
logic q;
} key1_in_l2h;
struct packed {
logic q;
} key0_in_l2h;
struct packed {
logic q;
} pwrb_l2h;
struct packed {
logic q;
} flash_wp_l_h2l;
struct packed {
logic q;
} ec_rst_l_h2l;
struct packed {
logic q;
} ac_present_h2l;
struct packed {
logic q;
} key2_in_h2l;
struct packed {
logic q;
} key1_in_h2l;
struct packed {
logic q;
} key0_in_h2l;
struct packed {
logic q;
} pwrb_h2l;
} sysrst_ctrl_reg2hw_key_intr_status_reg_t;

typedef struct packed {
logic d;
logic de;
Expand Down Expand Up @@ -474,29 +538,32 @@ package sysrst_ctrl_reg_pkg;

// Register -> HW type
typedef struct packed {
sysrst_ctrl_reg2hw_intr_state_reg_t intr_state; // [480:480]
sysrst_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [479:479]
sysrst_ctrl_reg2hw_intr_test_reg_t intr_test; // [478:477]
sysrst_ctrl_reg2hw_alert_test_reg_t alert_test; // [476:475]
sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl; // [474:459]
sysrst_ctrl_reg2hw_ulp_ac_debounce_ctl_reg_t ulp_ac_debounce_ctl; // [458:443]
sysrst_ctrl_reg2hw_ulp_lid_debounce_ctl_reg_t ulp_lid_debounce_ctl; // [442:427]
sysrst_ctrl_reg2hw_ulp_pwrb_debounce_ctl_reg_t ulp_pwrb_debounce_ctl; // [426:411]
sysrst_ctrl_reg2hw_ulp_ctl_reg_t ulp_ctl; // [410:410]
sysrst_ctrl_reg2hw_wkup_status_reg_t wkup_status; // [409:409]
sysrst_ctrl_reg2hw_key_invert_ctl_reg_t key_invert_ctl; // [408:397]
sysrst_ctrl_reg2hw_pin_allowed_ctl_reg_t pin_allowed_ctl; // [396:381]
sysrst_ctrl_reg2hw_pin_out_ctl_reg_t pin_out_ctl; // [380:373]
sysrst_ctrl_reg2hw_pin_out_value_reg_t pin_out_value; // [372:365]
sysrst_ctrl_reg2hw_key_intr_ctl_reg_t key_intr_ctl; // [364:351]
sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl; // [350:335]
sysrst_ctrl_reg2hw_auto_block_debounce_ctl_reg_t auto_block_debounce_ctl; // [334:318]
sysrst_ctrl_reg2hw_auto_block_out_ctl_reg_t auto_block_out_ctl; // [317:312]
sysrst_ctrl_reg2hw_com_pre_sel_ctl_mreg_t [3:0] com_pre_sel_ctl; // [311:292]
sysrst_ctrl_reg2hw_com_pre_det_ctl_mreg_t [3:0] com_pre_det_ctl; // [291:164]
sysrst_ctrl_reg2hw_com_sel_ctl_mreg_t [3:0] com_sel_ctl; // [163:144]
sysrst_ctrl_reg2hw_com_det_ctl_mreg_t [3:0] com_det_ctl; // [143:16]
sysrst_ctrl_reg2hw_com_out_ctl_mreg_t [3:0] com_out_ctl; // [15:0]
sysrst_ctrl_reg2hw_intr_state_reg_t intr_state; // [499:499]
sysrst_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [498:498]
sysrst_ctrl_reg2hw_intr_test_reg_t intr_test; // [497:496]
sysrst_ctrl_reg2hw_alert_test_reg_t alert_test; // [495:494]
sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl; // [493:478]
sysrst_ctrl_reg2hw_ulp_ac_debounce_ctl_reg_t ulp_ac_debounce_ctl; // [477:462]
sysrst_ctrl_reg2hw_ulp_lid_debounce_ctl_reg_t ulp_lid_debounce_ctl; // [461:446]
sysrst_ctrl_reg2hw_ulp_pwrb_debounce_ctl_reg_t ulp_pwrb_debounce_ctl; // [445:430]
sysrst_ctrl_reg2hw_ulp_ctl_reg_t ulp_ctl; // [429:429]
sysrst_ctrl_reg2hw_ulp_status_reg_t ulp_status; // [428:428]
sysrst_ctrl_reg2hw_wkup_status_reg_t wkup_status; // [427:427]
sysrst_ctrl_reg2hw_key_invert_ctl_reg_t key_invert_ctl; // [426:415]
sysrst_ctrl_reg2hw_pin_allowed_ctl_reg_t pin_allowed_ctl; // [414:399]
sysrst_ctrl_reg2hw_pin_out_ctl_reg_t pin_out_ctl; // [398:391]
sysrst_ctrl_reg2hw_pin_out_value_reg_t pin_out_value; // [390:383]
sysrst_ctrl_reg2hw_key_intr_ctl_reg_t key_intr_ctl; // [382:369]
sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl; // [368:353]
sysrst_ctrl_reg2hw_auto_block_debounce_ctl_reg_t auto_block_debounce_ctl; // [352:336]
sysrst_ctrl_reg2hw_auto_block_out_ctl_reg_t auto_block_out_ctl; // [335:330]
sysrst_ctrl_reg2hw_com_pre_sel_ctl_mreg_t [3:0] com_pre_sel_ctl; // [329:310]
sysrst_ctrl_reg2hw_com_pre_det_ctl_mreg_t [3:0] com_pre_det_ctl; // [309:182]
sysrst_ctrl_reg2hw_com_sel_ctl_mreg_t [3:0] com_sel_ctl; // [181:162]
sysrst_ctrl_reg2hw_com_det_ctl_mreg_t [3:0] com_det_ctl; // [161:34]
sysrst_ctrl_reg2hw_com_out_ctl_mreg_t [3:0] com_out_ctl; // [33:18]
sysrst_ctrl_reg2hw_combo_intr_status_reg_t combo_intr_status; // [17:14]
sysrst_ctrl_reg2hw_key_intr_status_reg_t key_intr_status; // [13:0]
} sysrst_ctrl_reg2hw_t;

// HW -> register type
Expand Down
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