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Refactor instruction definitions from macros to classes #302

Merged
merged 64 commits into from
Oct 5, 2023
Merged

Refactor instruction definitions from macros to classes #302

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21cfa0a
Reimplement B-Type RISC-V instruction as a template class
raccog Sep 22, 2023
cfee092
Rewrote declaration for `defineBType()`
raccog Sep 22, 2023
53de9f6
Reimplement I-Type RISC-V instruction as a template class
raccog Sep 22, 2023
8cec401
Reimplement I-Type32 RISC-V instruction as a template class
raccog Sep 22, 2023
f7fb3f1
Reimplement L-Type RISC-V instruction as a template class
raccog Sep 22, 2023
632aa9f
Added more RISC-V subclasses for `OpPart`, `Opcode,` and `Reg`
raccog Sep 22, 2023
a147b84
Add subclass for B-Type immediates
raccog Sep 22, 2023
aab1308
Add subclass for IType immediates and updated the IType class
raccog Sep 22, 2023
d59b8a3
Fix missing index field in RISC-V `Imm` subclasses
raccog Sep 22, 2023
5045aad
Rename `Imm` subclasses and update LTypeInstr subclass
raccog Sep 22, 2023
116850c
Reimplement IShiftType32 RISC-V instruction as a template class
raccog Sep 22, 2023
1dba5ee
Remove unnecessary functions
raccog Sep 25, 2023
8913b95
Add descriptions for RISC-V ISA classes
raccog Sep 25, 2023
a300ab6
Reimplement IShiftType64 RISC-V instruction as a template class
raccog Sep 25, 2023
c15efc0
Use RVOpcode class for RISC-V instruction classes
raccog Sep 25, 2023
c8b1d00
Reimplement RType RISC-V instruction as a template class
raccog Sep 25, 2023
1eae1dd
Reimplement S-Type RISC-V instruction as a template class
raccog Sep 25, 2023
42cce30
Rename RISC-V immediate classes to match their instruction type
raccog Sep 25, 2023
0e807de
Reimplement U-Type RISC-V instruction as a template class
raccog Sep 25, 2023
bec4676
Rewrite comments describing RISC-V immediate classes
raccog Sep 25, 2023
16d81d8
Reimplement J-Type RISC-V instruction as a template class
raccog Sep 25, 2023
39f2c85
Reimplement JALR-Type RISC-V instruction as a template class
raccog Sep 25, 2023
b250965
Fix field indices for S-Type RISC-V instructions
raccog Sep 25, 2023
d7986ef
Reimplement RISC-V pseudo-load instruction type as a template class
raccog Sep 26, 2023
63f72ae
Reimplement RISC-V pseudo-store instruction type as a template class
raccog Sep 26, 2023
908f352
Reimplement RISC-V CA-Type instruction as a template class
raccog Sep 26, 2023
3f4f82f
Run clang-format
raccog Sep 26, 2023
d5bda7c
Reimplement RISC-V CI-Type instruction as a template class
raccog Sep 26, 2023
9676bd4
Reimplement RISC-V CI-Type instruction as a template class
raccog Sep 26, 2023
b7fef3f
Add base classes for RISC-V instructions, registers, immediates, etc.
raccog Sep 26, 2023
1e44e21
Reimplement RISC-V CI-Type instruction as a template class
raccog Sep 26, 2023
56bf026
Remove unnecessary `shared_ptr` type
raccog Sep 26, 2023
5d05663
Fix comments for RISC-V compressed immediate classes
raccog Sep 26, 2023
5a9c59c
Update RVCImmADDI to be used for other instructions
raccog Sep 26, 2023
1fb5a5d
Reimplement RISC-V CI-Type instruction as a template class
raccog Sep 26, 2023
fb61584
Reimplement RISC-V CI-Type instruction as a template class
raccog Sep 26, 2023
b9eda8b
Fix C.ADDI and C.ADDIW immediates to be signed instead of unsigned
raccog Sep 26, 2023
a81953c
Remove unnecessary field index parameters for RISC-V immediate classes
raccog Sep 26, 2023
ad7bcc2
Fix comments for RISC-V compressed immediate class
raccog Sep 26, 2023
f8c6ff8
Remove unused macro for CI-Type RISC-V instructions
raccog Sep 26, 2023
28c6120
Reimplement RISC-V CINOP-Type instruction as a template class
raccog Sep 26, 2023
2cea1cd
Use RVOpcode type as parameter for RVInstruction classes
raccog Sep 26, 2023
fe3dfce
Add class for CSS-Type instructions
raccog Sep 26, 2023
07396f1
Reimplement c.swsp and c.fswsp instructions
raccog Sep 26, 2023
f824354
Reimplement c.sdsp and c.fsdsp instrutions
raccog Sep 26, 2023
f5747ab
Rename some RISC-V compressed register classes
raccog Sep 26, 2023
8cff43c
Reimplement c.lw and c.flw instructions
raccog Sep 26, 2023
98a29d7
Reimplement c.ld and c.fld instructions
raccog Sep 29, 2023
535af18
Reimplement c.sw, c.fsw, c.sd, and c.fsd instructions
raccog Sep 29, 2023
b29858c
Fix 5-bit RV-C registers to use proper apply() and decode() functions
raccog Sep 29, 2023
cc88a3a
Remove unnecessary std::make_shared types
raccog Sep 29, 2023
b3e7a69
Use shared_ptr constructor instead of make_shared for instructions
raccog Sep 29, 2023
214134c
Reimplement c.j and c.jal instructions
raccog Sep 29, 2023
d6e1c0d
Reimplement c.mv and c.add instructions
raccog Sep 29, 2023
599d272
Reimplement c.jr and c.jalr instructions
raccog Sep 29, 2023
cd8f422
Reimplement c.beqz and c.bnez instructions
raccog Sep 29, 2023
bd31486
Reimplement c.srli, c.srai, and c.andi instructions
raccog Sep 29, 2023
9ee06c9
Reimplement c.addi4spn instruction
raccog Sep 29, 2023
3750828
Change class comments to docstrings
raccog Sep 29, 2023
7ca8927
Fix some comments and change some class/variable names
raccog Sep 29, 2023
6f14d8b
Move op-specific classes to be nested within that op's class
raccog Oct 2, 2023
bda9123
Change small classes to structs
raccog Oct 2, 2023
ae8d69b
Remove RV/RVC prefix for nested structs
raccog Oct 3, 2023
ce87a56
Run clang-format
raccog Oct 4, 2023
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63 changes: 41 additions & 22 deletions src/assembler/rv64i_assembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -70,27 +70,41 @@ void RV64I_Assembler::enableExtI(const ISAInfoBase *isa,
{RV_I<Reg_T>::Options::shifts64BitVariant,
RV_I<Reg_T>::Options::LI64BitVariant});

instructions.push_back(IType32(Token("addiw"), 0b000));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrI32Type<Reg_T>(Token("addiw"), 0b000, isa)));

instructions.push_back(
IShiftType64(Token("slli"), RVISA::OPIMM, 0b001, 0b000000));
std::shared_ptr<_Instruction>(new RVInstrIShift64Type<Reg_T>(
Token("slli"), RVISA::OPIMM, 0b001, 0b000000, isa)));
instructions.push_back(
IShiftType64(Token("srli"), RVISA::OPIMM, 0b101, 0b000000));
std::shared_ptr<_Instruction>(new RVInstrIShift64Type<Reg_T>(
Token("srli"), RVISA::OPIMM, 0b101, 0b000000, isa)));
instructions.push_back(
IShiftType64(Token("srai"), RVISA::OPIMM, 0b101, 0b010000));

instructions.push_back(RType32(Token("addw"), 0b000, 0b0000000));
instructions.push_back(RType32(Token("subw"), 0b000, 0b0100000));
instructions.push_back(RType32(Token("sllw"), 0b001, 0b0000000));
instructions.push_back(RType32(Token("srlw"), 0b101, 0b0000000));
instructions.push_back(RType32(Token("sraw"), 0b101, 0b0100000));

instructions.push_back(LoadType(Token("lwu"), 0b110));
instructions.push_back(LoadType(Token("ld"), 0b011));
instructions.push_back(SType(Token("sd"), 0b011));

pseudoInstructions.push_back(PseudoLoad(Token("ld")));
pseudoInstructions.push_back(PseudoStore(Token("sd")));
std::shared_ptr<_Instruction>(new RVInstrIShift64Type<Reg_T>(
Token("srai"), RVISA::OPIMM, 0b101, 0b010000, isa)));

instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("addw"), 0b000, 0b0000000, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("subw"), 0b000, 0b0100000, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("sllw"), 0b001, 0b0000000, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("srlw"), 0b101, 0b0000000, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("sraw"), 0b101, 0b0100000, isa)));

instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrLType<Reg_T>(Token("lwu"), 0b110, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrLType<Reg_T>(Token("ld"), 0b011, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrSType<Reg_T>(Token("sd"), 0b011, isa)));

pseudoInstructions.push_back(std::shared_ptr<_PseudoInstruction>(
new RVPseudoInstrLoad<Reg_T>(Token("ld"))));
pseudoInstructions.push_back(std::shared_ptr<_PseudoInstruction>(
new RVPseudoInstrStore<Reg_T>(Token("sd"))));
pseudoInstructions.push_back(
std::shared_ptr<_PseudoInstruction>(new _PseudoInstruction(
Token("negw"), {RegTok, RegTok}, _PseudoExpandFunc(line) {
Expand All @@ -111,11 +125,16 @@ void RV64I_Assembler::enableExtM(const ISAInfoBase *isa,
_PseudoInstrVec &pseudoInstructions) {
RV_M<Reg_T>::enable(isa, instructions, pseudoInstructions);

instructions.push_back(RType32(Token("mulw"), 0b000, 0b0000001));
instructions.push_back(RType32(Token("divw"), 0b100, 0b0000001));
instructions.push_back(RType32(Token("divuw"), 0b101, 0b0000001));
instructions.push_back(RType32(Token("remw"), 0b110, 0b0000001));
instructions.push_back(RType32(Token("remuw"), 0b111, 0b0000001));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("mulw"), 0b000, 0b0000001, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("divw"), 0b100, 0b0000001, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("divuw"), 0b101, 0b0000001, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("remw"), 0b110, 0b0000001, isa)));
instructions.push_back(std::shared_ptr<_Instruction>(
new RVInstrR32Type<Reg_T>(Token("remuw"), 0b111, 0b0000001, isa)));
}

} // namespace Assembler
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