Merge pull request #19 from marnovandermaas/verilator_lint_fixes

Verilator lint fixes
microsoft · Feb 7, 2024 · 63bb154 · 63bb154
2 parents ad90fc7 + 3290c74
commit 63bb154
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Showing 3 changed files with 12 additions and 10 deletions.
diff --git a/rtl/cheri_decoder.sv b/rtl/cheri_decoder.sv
@@ -33,7 +33,7 @@ module cheri_decoder import cheri_pkg::*; # (
   output logic            cheri_multicycle_dec_o
   );
 
-  logic  [6:0] opcode;
+  logic  [6:0] unused_opcode;
   logic  [2:0] func3_op;
   logic  [6:0] func7_op;
   logic  [4:0] imm5_op;
@@ -44,14 +44,14 @@ module cheri_decoder import cheri_pkg::*; # (
   //  - fmt2: R-format, func3(14:12) = 0x0, func7(31:25) = subFunc, etc.
   //  - fmt3: I-format, func3(14:12) = 0x0, func7(31:25) = 0x7f, imm5(24:20) = subFunc
   //  - opcode [6:0] == 0x5b for all CHERI instructions
-  assign opcode   = instr_rdata_i[6:0];
-  assign func3_op = instr_rdata_i[14:12];
-  assign func7_op = instr_rdata_i[31:25];
-  assign imm5_op  = instr_rdata_i[24:20];
-  assign rd_op    = instr_rdata_i[11:7];
+  assign unused_opcode = instr_rdata_i[6:0];
+  assign func3_op      = instr_rdata_i[14:12];
+  assign func7_op      = instr_rdata_i[31:25];
+  assign imm5_op       = instr_rdata_i[24:20];
+  assign rd_op         = instr_rdata_i[11:7];
 
   always_comb begin
-    cheri_operator_o = 32'h0;
+    cheri_operator_o = OPDW'('h0);
 
     cheri_operator_o[CCSR_RW]         = cheri_opcode_en_i && (func3_op==0) && (func7_op==7'h01);
     cheri_operator_o[CSET_BOUNDS]     = cheri_opcode_en_i && (func3_op==0) && (func7_op==7'h08);

diff --git a/rtl/cheri_trvk_stage.sv b/rtl/cheri_trvk_stage.sv
@@ -101,7 +101,9 @@ module cheri_trvk_stage #(
       bitpos_q        <= 0;
       trvk_status     <= 1'b0;
       range_ok_q      <= 0;
-      trsv_addr_q     <= {'0, '0, '0};
+      trsv_addr_q[0]  <= 5'b0;
+      trsv_addr_q[1]  <= 5'b0;
+      trsv_addr_q[2]  <= 5'b0;
     end else begin
       // control signal per stage
       cpu_op_valid_q  <= {cpu_op_valid_q[1:0], cpu_op_valid};

diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv
@@ -386,8 +386,8 @@ module ibex_load_store_unit import ibex_pkg::*; import cheri_pkg::*; #(
   always_comb begin
     unique case (data_type_q)
       2'b00:       data_rdata_ext = rdata_w_ext;
-      2'b01:       data_rdata_ext = rdata_h_ext;
-      2'b10,2'b11: data_rdata_ext = rdata_b_ext;
+      2'b01:       data_rdata_ext = {1'b0, rdata_h_ext};
+      2'b10,2'b11: data_rdata_ext = {1'b0, rdata_b_ext};
       default:     data_rdata_ext = rdata_w_ext;
     endcase // case (data_type_q)
   end