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[spi_device] Add separate constraints for TPM and fast passthrough #21595

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merged 4 commits into from
Feb 22, 2024

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@a-will a-will commented Feb 21, 2024

Add constraints that are specific to TPM and fast passthrough commands. This might be excessive, but now there are five constraints modes:

  • 50 MHz, full-cycle sampling, no passthrough, flash I/O delays
  • 25 MHz, half-cycle sampling, no passthrough, flash I/O delays
  • 25 MHz, half-cycle sampling, TPM I/O delays
  • 25 MHz, full-cycle sampling, all passthrough, flash I/O delays
  • 40 MHz, full-cycle sampling, pipelined passthrough only, flash I/O delays

We may be able to consolidate these, but we'll likely want to take a look at the data first.

In addition to the new constraint sets, some generic mode-specific exceptions get removed, and we select IOA7 as the only timed pad for SPI TPM's CSB. We should confirm that this is the correct chosen pad.

Finally, just a note, but for real synthesis, the pads should be set to the appropriate configuration to effect the intended data sheet. The defaults (e.g. minimum drive strength) will likely lead to very long pad delays used in analysis.

Since generic mode has been removed, also remove SDCs related to it.

Signed-off-by: Alexander Williams <[email protected]>
Create a separate timing for fast read commands for passthrough. The
commands that use the fast read pipeline can have higher clock rates,
while the combinatorial path cannot meet timing at those rates.

Change the target for slow commands to 24 MHz, and target 33+ MHz for
fast commands. The latter is currently overconstrained to 40 MHz.

Signed-off-by: Alexander Williams <[email protected]>
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a-will commented Feb 21, 2024

Related to the TPM CSB discussion: #21538

Create separate constraints for the TPM module. The TPM specification
has some potentially more strict requirements for CSB on the device side
than would be required for the SPI flash operations.

Signed-off-by: Alexander Williams <[email protected]>
Relax timing requirements by selecting IOA7 as the sole pad required to
meet timing for SPI Device's TPM mode CSB.

Signed-off-by: Alexander Williams <[email protected]>
@a-will a-will marked this pull request as ready for review February 21, 2024 22:33
@a-will a-will linked an issue Feb 21, 2024 that may be closed by this pull request
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Thanks @a-will!

@a-will a-will merged commit 5830797 into lowRISC:master Feb 22, 2024
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@a-will a-will deleted the spid-sdc branch February 22, 2024 20:51
@a-will a-will mentioned this pull request Feb 27, 2024
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[spi_device] Optimize CS pin on at most 1-2 pinmux paths
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