[flash_ctrl] Change FIFO interrupts to status type #21226
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@msfschaffner flash_ctrl block dv cleanup is updated here |
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Only event type interrupts can be cleared by writing 1 to them since they are W1C. Status type interrupts cannot be cleared that way since they are RO for SW. Instead, the underlying cause has to be addressed, such as reading out a FIFO if it is above a certain watermark level. Signed-off-by: Michael Schaffner <[email protected]>
This allows to specify whether a status type interrupt is expected to assert by default. The field is intended to be used in generated DV collateral, primarily. Signed-off-by: Michael Schaffner <[email protected]>
This adds the option to mute status type IRQs in the testutils ISR, given that an IP contains status type interrupts. Signed-off-by: Michael Schaffner <[email protected]>
Need to increase the version to 2.0.0 due to a SW visible CSR change. The D/V stages should be straightforward to recertify. Signed-off-by: Michael Schaffner <[email protected]>
This fixes lowRISC#21211 Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Jaedon Kim <[email protected]> Signed-off-by: Michael Schaffner <[email protected]>
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The first two commits patch up common infrastructure:
cip_base_vseqneeds to be adjusted so that it does not fail when status interrupts remain asserted (since they cannot be cleared via a write to theINTR_STATEregister.defaultis added to the interrupt declaration in the IP Hjson file. This allows us to define what the default expectation of the interrupt should be during automatically generated tests such as thechip_plic_all_irqstop-level test. That test is aligned to treat status interrupts differently now. In particular, the ones that are asserted by default will not be enabled until that specific interrupt is being tested.The last two commits are the changes in
flash_ctrl, aligning the interrupt type behavior according to #21211.This fixes #21211