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[chip-test] chip_sw_pwrmgr_deep_sleep_por_reset #20133

Closed
9 of 10 tasks
matutem opened this issue Oct 20, 2023 · 1 comment
Closed
9 of 10 tasks

[chip-test] chip_sw_pwrmgr_deep_sleep_por_reset #20133

matutem opened this issue Oct 20, 2023 · 1 comment
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@matutem
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Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation

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matutem commented Oct 20, 2023 •
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Test point name

chip_sw_pwrmgr_deep_sleep_por_reset

Host side component

SystemVerilog+Rust

OpenTitanTool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation Targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

matutem

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • HJSON test plan updated with test name (so it shows up in the dashboard)
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression
@matutem matutem added Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation labels Oct 20, 2023
matutem added a commit to matutem/opentitan that referenced this issue Oct 20, 2023
@matutem
[sival,pwrmgr] Create sim_dv sleep por reset tests
9ac93d6 
Create chip_sw_pwrmgr_sleep_por_reset.
Create chip_sw_pwrmgr_deep_sleep_por_reset.
These tests were part of the *sleep_all_reset_reqs tests, but are moved
to their own test to simplify these tests.
They only run in sim_dv in this commit, but the rust side is in development.

Addresses lowRISC#20133
Addresses lowRISC#20134

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit to matutem/opentitan that referenced this issue Oct 20, 2023
@matutem
[sival,pwrmgr] Create sim_dv sleep por reset tests
0d430d2 
Create chip_sw_pwrmgr_sleep_por_reset.
Create chip_sw_pwrmgr_deep_sleep_por_reset.
These tests were part of the *sleep_all_reset_reqs tests, but are moved
to their own test to simplify these tests.
They only run in sim_dv in this commit, but the rust side is in development.

Addresses lowRISC#20133
Addresses lowRISC#20134

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit to matutem/opentitan that referenced this issue Oct 21, 2023
@matutem
[sival,pwrmgr] Rework the various sleep_all_reset tests
174a2b7 
Create a library to share the C code.
Remove some redundant test cases.
Avoid memory overwrite, instead have the CPU sequence the reset cases.
Adjust SV sequence so it can deal with all three tests.

Addresses lowRISC#20133
Addresses lowRISC#20134

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit to matutem/opentitan that referenced this issue Oct 23, 2023
@matutem
[sival,pwrmgr] Create sim_dv sleep por reset tests
bb55811 
Create chip_sw_pwrmgr_sleep_por_reset.
Create chip_sw_pwrmgr_deep_sleep_por_reset.
These tests were part of the *sleep_all_reset_reqs tests, but are moved
to their own test to simplify these tests.
They only run in sim_dv in this commit, but the rust side is in development.

Addresses lowRISC#20133
Addresses lowRISC#20134

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit to matutem/opentitan that referenced this issue Oct 23, 2023
@matutem
[sival,pwrmgr] Rework the various sleep_all_reset tests
5a49fd0 
Create a library to share the C code.
Remove some redundant test cases.
Avoid memory overwrite, instead have the CPU sequence the reset cases.
Adjust SV sequence so it can deal with all three tests.

Addresses lowRISC#20133
Addresses lowRISC#20134

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit that referenced this issue Oct 23, 2023
@matutem
[sival,pwrmgr] Create sim_dv sleep por reset tests
59edcb4 
Create chip_sw_pwrmgr_sleep_por_reset.
Create chip_sw_pwrmgr_deep_sleep_por_reset.
These tests were part of the *sleep_all_reset_reqs tests, but are moved
to their own test to simplify these tests.
They only run in sim_dv in this commit, but the rust side is in development.

Addresses #20133
Addresses #20134

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit that referenced this issue Oct 23, 2023
@matutem
[sival,pwrmgr] Rework the various sleep_all_reset tests
2380df3 
Create a library to share the C code.
Remove some redundant test cases.
Avoid memory overwrite, instead have the CPU sequence the reset cases.
Adjust SV sequence so it can deal with all three tests.

Addresses #20133
Addresses #20134

Signed-off-by: Guillermo Maturana <[email protected]>
@matutem matutem self-assigned this Dec 26, 2023
@matutem
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matutem commented Dec 26, 2023

This was done in #20153.

@matutem matutem closed this as completed Dec 26, 2023
@matutem matutem mentioned this issue Feb 26, 2024
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@matutem matutem mentioned this issue Mar 8, 2024
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