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[rv_plic,dv] Implement assertions EdgeTriggeredIp_A
and EdgeTriggeredIpWithClaim_A
#17412
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IP:rv_plic
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Assigning currently to @msfschaffner to decide who to forward assign to. |
I don't think this is critical right now, since we already test the PLIC quite extensively at the system level. I think we can defer this . |
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This was referenced Feb 23, 2024
Turns out that these assertions should have been removed from the testplan when we removed the option for interrupts to use edge triggered signalling. |
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Feb 23, 2024
These two assertions tested edge triggered interrupts, but since the option of edge signalling has been removed a long time ago, these two testplan entries are stale and can be removed. Fixes lowRISC#17412 Signed-off-by: Michael Schaffner <[email protected]>
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These two assertions tested edge triggered interrupts, but since the option of edge signalling has been removed a long time ago, these two testplan entries are stale and can be removed. Fixes lowRISC#17412 Signed-off-by: Michael Schaffner <[email protected]>
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These two assertions tested edge triggered interrupts, but since the option of edge signalling has been removed a long time ago, these two testplan entries are stale and can be removed. Fixes #17412 Signed-off-by: Michael Schaffner <[email protected]>
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These two assertions tested edge triggered interrupts, but since the option of edge signalling has been removed a long time ago, these two testplan entries are stale and can be removed. Fixes lowRISC#17412 Signed-off-by: Michael Schaffner <[email protected]>
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Labels
Component:DV
DV issue: testbench, test case, etc.
Earlgrey-PROD Candidate
Temporary label to triage issues into Earlgrey-PROD Milestones
IP:rv_plic
Priority:P2
Priority: medium
Those two assertions are defined in
rv_plic_fpv_testplan.hjson.tpl
, but they are not implemented.The text was updated successfully, but these errors were encountered: