[rv_plic] V2(S) Signoff

[msfschaffner]

Description

Ensure V2(S) signoff criteria are still maintained (this is not a focus area block).

[msfschaffner]

This issue is WIP.

Commits since Earlgrey-ES tapeout

$ git rev-parse --short HEAD

c5faa9b

$ git log Earlgrey-M2.5.2-RC0..HEAD --oneline hw/ip_templates/rv_plic

4a9a881 [topgen] Pass topname key/value pair to ipgen
de31bdf [reggen] Remove the devmode input
620bd34 [rv_plic,sival] List rv_plic features in its hjson file
eee74c3 [ip_templates,hjson] Remove clutter
7688e71 [reggen] Add initial support for version and cip_id hjson fields
fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
0ba10b3 [reggen] Add CIP_IDs and bump all major versions

Issues closed since the Earlgrey-ES tapeout

• [plic] Review latest PLIC spec (1.0.0-rc5) #14839
  • This was a review task to make sure there are no alignments needed in order to be compliant with the RISC-V PLIC 1.0.0 spec
• [rv_plic,dv] Implement assertions EdgeTriggeredIp_A and EdgeTriggeredIpWithClaim_A #17412
  • stale SVAs in the testplan, will be removed in [rv_plic/fpv] Remove stale testplan entries #21655

Currently open issues

• [chip-test] chip_sw_plic_sw_irq #21414
  • sival issue
• [doc] Add human-readable names and descriptions to remaining blocks #17307
  • general doc improvement, not needed for D2S.
• [chip] plic_all_irqs test processes *_irq_serviced incorrectly #15584
  • this describes behavior that was observed in top-level tests: the interrupt signal propagation delays are dependent on the peripheral clock frequency. I don't think we should and will be able to change anything for PROD here, since this behavior is inherent to the chosen implementation.
• [top/doc] Autogenerated tables for top-specific IP #12848
  • this is a top-level doc improvement, not needed for D2S.
• [tracking] Use ipgen to produce templated IPs #8440
  • this IP is already IPgen'd
• [all] interrupt consolidation #3421
  • this is a future improvement at the system level and no change is needed in rv_plic
• [reggen] Changing multireg structure #270
  • very old issue about adding support for different multireg structures with nested register arrays. this is not within scope for PROD.

Coverage report from

name	pass_rate	stimuli_cov	coi_cov	prove_cov
rv_plic_fpv	100.00 %	71.23 %	93.31 %	69.94 %

Summary

There have been no hardware changes since the ES tapeout, and no critical bugs have been found.
The recommendation is hence to leave this IP at the V2 stage claimed in its Hjson file:

opentitan/hw/ip_templates/rv_plic/data/rv_plic.hjson.tpl

Lines 22 to 30 in c5faa9b

	{
	version: "1.0.0",
	life_stage: "L1",
	design_stage: "D3",
	verification_stage: "V2",
	dif_stage: "S2",
	commit_id: "",
	notes: "Use FPV to perform block level verification.",
	}

[rswarbrick]

I'm convinced!

About the coverage report, I believe that verification of rv_plic is FPV-based (e.g. looking at hw/ip_templates/rv_plic/doc/dv/README.md). So I'm not sure we're going to have any way to make a "simulation-based coverage report" in the way we'd do for most blocks.

[msfschaffner]

There is a way to extract coverage from FPV, and I was going to rerun after I looked at those missing assertions that are mentioned in the issues.

[msfschaffner]

Reran FPV and all assertions pass.
COI coverage is above 75% which we require for this milestone.
Given that this block is heavily used in top-level tests as well, and there have been no RTL changes nor issues reported since the ES tapeout, I think we can sign this block off.