[top_earlgrey] Add fourth I2C

The following files were edited manually:
- hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson
- hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el
- hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv
- hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv
- hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv
- hw/top_earlgrey/cdc/cdc_waivers.data.tcl
- hw/top_earlgrey/data/chip_conn_testplan.hjson
- hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson
- hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson
- hw/top_earlgrey/data/pins_cw310.xdc
- hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc
- hw/top_earlgrey/data/pins_cw341.xdc
- hw/top_earlgrey/data/top_earlgrey.hjson
- hw/top_earlgrey/data/xbar_peri.hjson
- hw/top_earlgrey/doc/datasheet.md
- hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg
- hw/top_earlgrey/dv/chip_sim_cfg.hjson
- hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg
- hw/top_earlgrey/dv/env/chip_common_pkg.sv
- hw/top_earlgrey/dv/env/chip_if.sv
- hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv
- hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv
- hw/top_earlgrey/dv/tb/tb.sv
- hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv
- hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv
- hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv
- hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc
- rules/const.bzl
- sw/device/lib/dif/dif_alert_handler_unittest.cc
- sw/device/lib/dif/dif_rstmgr.c
- sw/device/lib/dif/dif_rv_plic_unittest.cc
- sw/device/lib/testing/i2c_testutils.c
- sw/device/lib/testing/json/pinmux.h
- sw/device/tests/alert_handler_lpg_reset_toggle.c
- sw/device/tests/i2c_target_test.c
- sw/device/tests/pmod/i2c_host_eeprom_test.c
- sw/device/tests/pmod/i2c_host_fram_test.c
- sw/device/tests/power_virus_systemtest.c
- sw/device/tests/rstmgr_alert_info_test.c
- sw/device/tests/rstmgr_sw_rst_ctrl_test.c
- sw/device/tests/sim_dv/all_escalation_resets_test.c
- sw/device/tests/sim_dv/i2c_device_tx_rx_test.c
- sw/device/tests/sim_dv/i2c_host_tx_rx_test.c
- sw/host/opentitanlib/src/otp/alert_handler.rs

Changes to all other files were autogenerated by running the following
commands:
- make -C hw
- util/cmdgen.py -u '**/*.md'
- util/regtool.py \
    hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \
    -D -o alert_handlers_regs.h
- bindgen alert_handlers_regs.h -o \
    sw/host/opentitanlib/src/otp/alert_handler_regs.rs

See issue #19505 for how to compute the values in
`hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`.

The following top-level tests were run for a basic integration check of
the added I2C instance, and the tests pass (for one invocation with the
configured number of reseeds):
- chip_sw_alert_handler_lpg_reset_toggle
- chip_sw_all_escalation_resets
- chip_sw_i2c_device_tx_rx
- chip_sw_i2c_host_tx_rx_idx3
- chip_sw_rstmgr_alert_info
- chip_sw_rstmgr_sw_rst

`chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the
rate and signature of this failure matches the one found in the nightly
regressions, so this commit doesn't seem to make this worse.

`chip_sw_power_virus` still fails but the signature of this failure
matches the one found in the nightly regressions, so this commit doesn't
seem to have broken it.

The remaining top-level tests that were modified don't run in
simulation, so I didn't check them for this commit.

Signed-off-by: Andreas Kurth <[email protected]>

hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson

@@ -187,19 +187,19 @@
                 },
                 {
                     name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV",
-                    value: "0xf23b13fb",
+                    value: "0xf2792a29",
                 },
                 {
                     name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD",
-                    value: "0x9c933414",
+                    value: "0x9cd10dc6",
                 },
                 {
                     name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END",
-                    value: "0x68d8d091",
+                    value: "0x689ae943",
                 },
                 {
                     name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA",
-                    value: "0x36ed9cb0",
+                    value: "0x36afa562",
                 }
             ],
         }

hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el

@@ -15,6 +15,10 @@
 CHECKSUM: "258095983 1288805244"
 INSTANCE: tb.dut
 ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_i2c3_n [0] "logic resets_o.rst_i2c3_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_i2c3_n [0] "logic resets_o.rst_i2c3_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
 Toggle 0to1 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]"
 ANNOTATION: "VC_COV_UNR"
 Toggle 1to0 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]"

hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv

@@ -42,6 +42,7 @@ package rstmgr_env_pkg;
     "u_d0_i2c0",
     "u_d0_i2c1",
     "u_d0_i2c2",
+    "u_d0_i2c3",
     "u_d0_lc",
     "u_d0_lc_io",
     "u_d0_lc_io_div2",

hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv

@@ -113,6 +113,7 @@ class rstmgr_scoreboard extends cip_base_scoreboard #(
       "5": blocked = `gmv(ral.sw_rst_regwen[5]) == 0;
       "6": blocked = `gmv(ral.sw_rst_regwen[6]) == 0;
       "7": blocked = `gmv(ral.sw_rst_regwen[7]) == 0;
+      "8": blocked = `gmv(ral.sw_rst_regwen[8]) == 0;
       default:
         `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", ral_name))
     endcase

hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv

@@ -49,6 +49,7 @@ module rstmgr_bind;
     .parent_rst_n(rst_sys_src_n[1]),
     .ctrl_ns(reg2hw.sw_rst_ctrl_n),
     .rst_ens({
+      rst_en_o.i2c3[1] == prim_mubi_pkg::MuBi4True,
       rst_en_o.i2c2[1] == prim_mubi_pkg::MuBi4True,
       rst_en_o.i2c1[1] == prim_mubi_pkg::MuBi4True,
       rst_en_o.i2c0[1] == prim_mubi_pkg::MuBi4True,
@@ -59,6 +60,7 @@ module rstmgr_bind;
       rst_en_o.spi_device[1] == prim_mubi_pkg::MuBi4True
     }),
     .rst_ns({
+      resets_o.rst_i2c3_n[1],
       resets_o.rst_i2c2_n[1],
       resets_o.rst_i2c1_n[1],
       resets_o.rst_i2c0_n[1],

hw/top_earlgrey/cdc/cdc_waivers.data.tcl

@@ -5,6 +5,8 @@
 # Verix CDC waiver file
 
 set_rule_status -rule {CNTL} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK") && (ReceivingFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic.q_o[0]") && (Signal =~ "IO*") && (Association == "None") && (SyncDepth == "2") && (SyncFlop == "top_earlgrey.u_gpio.gen_filter[0].u_filter.gen_async.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic.q_o[0]")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD}
+set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c3.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD}
+set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c3.i2c_core.sda_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD}
 set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c2.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD}
 set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c2.i2c_core.sda_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD}
 set_rule_status -rule {DATA} -expression {(ReceivingFlop == "top_earlgrey.u_i2c1.i2c_core.scl_rx_val[0]") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD}