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[bazel,otp_ctrl] OWNER_SW_CFG_ROM_ALERT_DIGEST_*
values are hardcoded
#19505
Comments
@andreaskurth Just to be clear, you are saying that |
IIUC, the image files get updated when I had to do this manually multiple times, so I threw together a simple script to do the job (expects to live under #!/usr/bin/env python3
import inspect
import hjson
import re
import subprocess as sp
import pathlib
import tempfile
REPO_ROOT = pathlib.Path(__file__).parent.parent.resolve()
def abspath(relpath: str):
return str(REPO_ROOT / relpath)
# Generate temporary `alert_handler_regs.h` from `alert_handler.hjson`.
alert_handler_regs_h = tempfile.NamedTemporaryFile(prefix='alert_handler_regs',
suffix='.h')
sp.run([abspath('util/regtool.py'),
abspath('hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson'),
'-D',
'-o',
alert_handler_regs_h.name],
check=True)
# Generate `alert_handler_regs.rs` from temporary `alert_handler_regs.h`.
alert_handler_regs_rs = abspath('sw/host/opentitanlib/src/otp/alert_handler_regs.rs')
sp.run(['bindgen',
alert_handler_regs_h.name,
'-o',
alert_handler_regs_rs],
check=True)
# Prepend license header, which `bindgen` removed, to `alert_handler_regs.rs`.
with open(alert_handler_regs_rs, 'r') as f:
data = f.read()
with open(alert_handler_regs_rs, 'w') as f:
header = '''// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
'''
header = inspect.cleandoc(header) + '\n\n'
f.write(header + data)
# Compute new alert digest values for `otp_ctrl_img_owner_sw_cfg.hjson`.
otp_ctrl_img_owner_sw_cfg = abspath(
'hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson')
proc = sp.run(['bazel',
'run',
'//sw/host/opentitantool',
'--',
'--rcfile=""',
'otp',
'alert-digest',
otp_ctrl_img_owner_sw_cfg],
capture_output=True, check=True)
data = hjson.loads(proc.stdout.decode())
items = data['partitions'][0]['items']
cfg = {i['name']: hex(i['value']) for i in items}
# Replace alert digest values in `otp_ctrl_img_owner_sw_cfg.hjson` while
# keeping the rest of the file intact.
with open(otp_ctrl_img_owner_sw_cfg, 'r') as f:
raw_file = f.read()
for name, value in cfg.items():
name_idx = raw_file.find(name)
trailer = re.sub(r'value:\s*"?0x[a-fA-F0-9]+"?',
f'value: "{value}"',
raw_file[name_idx:],
count=1)
raw_file = raw_file[:name_idx] + trailer
with open(otp_ctrl_img_owner_sw_cfg, 'w') as f:
f.write(raw_file) Maybe parts of this script could be used to resolve this issue |
The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue lowRISC#19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth <[email protected]>
The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue lowRISC#19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth <[email protected]>
The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - rules/const.bzl - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue lowRISC#19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth <[email protected]>
The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - rules/const.bzl - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue lowRISC#19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth <[email protected]>
The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/doc/registers.md.tpl - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - rules/const.bzl - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue lowRISC#19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. To update the expected CRC32 values in `sw/host/opentitanlib/src/otp/alert_handler.rs` run `bazel test //sw/host/opentitanlib:opentitanlib_test` and extract the expected values from the log file. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth <[email protected]>
The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/doc/registers.md.tpl - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - rules/const.bzl - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue lowRISC#19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. To update the expected CRC32 values in `sw/host/opentitanlib/src/otp/alert_handler.rs` run `bazel test //sw/host/opentitanlib:opentitanlib_test` and extract the expected values from the log file. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth <[email protected]>
The following files were edited manually: - hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson - hw/ip_templates/rstmgr/doc/registers.md.tpl - hw/ip_templates/rstmgr/dv/cov/rstmgr_unr_excl.el - hw/ip_templates/rstmgr/dv/env/rstmgr_env_pkg.sv - hw/ip_templates/rstmgr/dv/env/rstmgr_scoreboard.sv - hw/ip_templates/rstmgr/dv/sva/rstmgr_bind.sv - hw/top_earlgrey/cdc/cdc_waivers.data.tcl - hw/top_earlgrey/data/chip_conn_testplan.hjson - hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson - hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson - hw/top_earlgrey/data/pins_cw310.xdc - hw/top_earlgrey/data/pins_cw341.xdc - hw/top_earlgrey/data/top_earlgrey.hjson - hw/top_earlgrey/data/xbar_peri.hjson - hw/top_earlgrey/doc/datasheet.md - hw/top_earlgrey/doc/top_earlgrey_block_diagram.svg - hw/top_earlgrey/dv/chip_sim_cfg.hjson - hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg - hw/top_earlgrey/dv/env/chip_common_pkg.sv - hw/top_earlgrey/dv/env/chip_if.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv - hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv - hw/top_earlgrey/dv/tb/tb.sv - hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv - hw/top_earlgrey/formal/conn_csvs/rstmgr_rst_en.csv - hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc - rules/const.bzl - sw/device/lib/dif/dif_alert_handler_unittest.cc - sw/device/lib/dif/dif_rstmgr.c - sw/device/lib/dif/dif_rv_plic_unittest.cc - sw/device/lib/testing/i2c_testutils.c - sw/device/lib/testing/json/pinmux.h - sw/device/tests/alert_handler_lpg_reset_toggle.c - sw/device/tests/i2c_target_test.c - sw/device/tests/pmod/i2c_host_eeprom_test.c - sw/device/tests/pmod/i2c_host_fram_test.c - sw/device/tests/power_virus_systemtest.c - sw/device/tests/rstmgr_alert_info_test.c - sw/device/tests/rstmgr_sw_rst_ctrl_test.c - sw/device/tests/sim_dv/all_escalation_resets_test.c - sw/device/tests/sim_dv/i2c_device_tx_rx_test.c - sw/device/tests/sim_dv/i2c_host_tx_rx_test.c - sw/host/opentitanlib/src/otp/alert_handler.rs Changes to all other files were autogenerated by running the following commands: - make -C hw - util/cmdgen.py -u '**/*.md' - util/regtool.py \ hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson \ -D -o alert_handlers_regs.h - bindgen alert_handlers_regs.h -o \ sw/host/opentitanlib/src/otp/alert_handler_regs.rs See issue lowRISC#19505 for how to compute the values in `hw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson`. To update the expected CRC32 values in `sw/host/opentitanlib/src/otp/alert_handler.rs` run `bazel test //sw/host/opentitanlib:opentitanlib_test` and extract the expected values from the log file. The following top-level tests were run for a basic integration check of the added I2C instance, and the tests pass (for one invocation with the configured number of reseeds): - chip_sw_alert_handler_lpg_reset_toggle - chip_sw_all_escalation_resets - chip_sw_i2c_device_tx_rx - chip_sw_i2c_host_tx_rx_idx3 - chip_sw_rstmgr_alert_info - chip_sw_rstmgr_sw_rst `chip_sw_all_escalation_resets` fails for ca. 3 % of the seeds but the rate and signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to make this worse. `chip_sw_power_virus` still fails but the signature of this failure matches the one found in the nightly regressions, so this commit doesn't seem to have broken it. The remaining top-level tests that were modified don't run in simulation, so I didn't check them for this commit. Signed-off-by: Andreas Kurth <[email protected]>
The values of
OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV
,OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD
,OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END
, andOWNER_SW_CFG_ROM_ALERT_DIGEST_RMA
are hardcoded inhw/ip/otp_ctrl/data/otp_ctrl_img_owner_sw_cfg.hjson
. When changing the alert handler configuration and re-generating the RTL, that HJSON file does not get updated. Manually updatingsw/host/opentitanlib/src/otp/alert_handler_regs.rs
(see #19501) and restarting simulation does not update the HJSON either.The text was updated successfully, but these errors were encountered: