[ImportVerilog] Support assignment patterns with integer type #7646
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Add a `moore.builtin.clog2` op and use it to convert `$clog2` calls in ImportVerilog.
Allow `'{...}` assignment patterns to be used to assign integer values.
Slang already computes the value for each element in the resulting type.
All that's needed is a concat with the right operand order.
| @@ -655,6 +655,8 @@ module Expressions; | |||
| bit [1:0][31:0] arrayInt; | |||
| // CHECK: %uarrayInt = moore.variable : <uarray<2 x i32>> | |||
| bit [31:0] uarrayInt [2]; | |||
| // CHECK: %m = moore.variable : <l4> | |||
| logic [3:0] m; | |||
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If you change this to logic [0:3] the concat element order reverses as well, right?
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Hmmm good point. I'm not sure what the expected bit order would be in that case 🤔. Intuitively that would make sense. But I also remember the standard mentioning that the array direction doesn't really matter -- e.g. you can't reverse bits by assigning a [0:3] array to a [3:0] array, people usually resort to the streaming operators for that. Time to look through the standard some more 😉
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Oh I just realized that the assignment patterns talk about element indices explicitly: '{3: 'x} will assign bit index 3, regardless of whether the array was declared as [3:0] or [0:3]. And since the Moore dialect removes array directionality (if it becomes important we'll just emit flip ops in the right places), the concat should work as it is now (bit index 3 is always in the same location in the Moore dialect).
Allow
'{...}assignment patterns to be used to assign integer values. Slang already computes the value for each element in the resulting type. All that's needed is a concat with the right operand order.