[FIRRTL] Add verifier of single MarkDUTAnnotation (#7633)

Add a CircuitOp verifier that guarantees that there is zero or one modules annotated with a `MarkDUTAnnotation`. This is important as many passes assume that this is the case. Moving this check into a verifier means that logic checking this behavior in each pass can be removed. I am slightly concerned of the performance cost of doing this as examining the annotations is non-trivial and this will cause that examination to now happen more often. Signed-off-by: Schuyler Eldridge <[email protected]>
llvm · Sep 26, 2024 · 3ffc39c · 3ffc39c
1 parent ee8e605
commit 3ffc39c
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diff --git a/lib/Dialect/FIRRTL/FIRRTLOps.cpp b/lib/Dialect/FIRRTL/FIRRTLOps.cpp
@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "circt/Dialect/FIRRTL/FIRRTLOps.h"
+#include "circt/Dialect/FIRRTL/AnnotationDetails.h"
 #include "circt/Dialect/FIRRTL/CHIRRTLDialect.h"
 #include "circt/Dialect/FIRRTL/FIRRTLAnnotations.h"
 #include "circt/Dialect/FIRRTL/FIRRTLAttributes.h"
@@ -627,14 +628,32 @@ LogicalResult CircuitOp::verifyRegions() {
     return success();
   };
 
+  SmallVector<FModuleOp, 1> dutModules;
   for (auto &op : *getBodyBlock()) {
+    // Verify modules.
+    if (auto moduleOp = dyn_cast<FModuleOp>(op)) {
+      if (AnnotationSet(moduleOp).hasAnnotation(dutAnnoClass))
+        dutModules.push_back(moduleOp);
+      continue;
+    }
+
     // Verify external modules.
     if (auto extModule = dyn_cast<FExtModuleOp>(op)) {
       if (verifyExtModule(extModule).failed())
         return failure();
     }
   }
 
+  // Error if there is more than one design-under-test.
+  if (dutModules.size() > 1) {
+    auto diag = dutModules[0]->emitOpError()
+                << "is annotated as the design-under-test (DUT), but other "
+                   "modules are also annotated";
+    for (auto moduleOp : ArrayRef(dutModules).drop_front())
+      diag.attachNote(moduleOp.getLoc()) << "is also annotated as the DUT";
+    return failure();
+  }
+
   return success();
 }
 

diff --git a/test/Dialect/FIRRTL/errors.mlir b/test/Dialect/FIRRTL/errors.mlir
@@ -2561,3 +2561,33 @@ firrtl.circuit "MainNotModule" {
     return
   }
 }
+
+// -----
+
+firrtl.circuit "MultipleDUTModules" {
+  firrtl.module @MultipleDUTModules() {}
+  // expected-error @below {{is annotated as the design-under-test}}
+  firrtl.module @Foo() attributes {
+    annotations = [
+      {
+        class = "sifive.enterprise.firrtl.MarkDUTAnnotation"
+      }
+    ]
+  } {}
+  // expected-note @below {{is also annotated as the DUT}}
+  firrtl.module @Bar() attributes {
+    annotations = [
+      {
+        class = "sifive.enterprise.firrtl.MarkDUTAnnotation"
+      }
+    ]
+  } {}
+  // expected-note @below {{is also annotated as the DUT}}
+  firrtl.module @Baz() attributes {
+    annotations = [
+      {
+        class = "sifive.enterprise.firrtl.MarkDUTAnnotation"
+      }
+    ]
+  } {}
+}