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V.2 #2

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35bfdca
new brannch v1
JacobG111 Oct 31, 2024
ac9fdfb
selected LV bypass caps values
JacobG111 Oct 31, 2024
d480dc8
finalized layout, fixed prechagre res dimensions
JacobG111 Oct 31, 2024
dfd161b
removed LDO fuse, added series resistors, added to sch explinations, …
JacobG111 Nov 1, 2024
71bf6f9
oops forgot to save last time, attempt two
JacobG111 Nov 1, 2024
fc7c926
added silkscreen title
JacobG111 Nov 2, 2024
d40f61f
passes ERC now, added dimensions on layout editor
JacobG111 Nov 2, 2024
65b13fc
fixed optocoupler data sheet link
JacobG111 Nov 2, 2024
5cb4f92
added connector labels
JacobG111 Nov 2, 2024
d810f7a
11/2 fixed incorrect footprint and symbol
Tony5427 Nov 2, 2024
0f155d7
HV and trace routing fixes
Tony5427 Nov 2, 2024
a7c65bb
dimension checks and silkscreen additions
Tony5427 Nov 2, 2024
f8a3987
revert LDO HV resistor position
Tony5427 Nov 2, 2024
d041397
adjusted HVGND position to be more centralized, added backplane trace…
JacobG111 Nov 2, 2024
1a3d2e7
refix HVGND isolation issue
Tony5427 Nov 2, 2024
c785aac
fixed positioning of silkscreen labels for HV 1x3 connector
JacobG111 Nov 2, 2024
18d9a9c
fixed silkscreen and edge cuts issues
Tony5427 Nov 2, 2024
65d0e81
initial sch and layout changes w/ test points
JacobG111 Nov 6, 2024
358797b
finished layout w/ all testpoints
JacobG111 Nov 6, 2024
8359acf
improved tp labels, moved vias on the tp rather than next to the tp, …
JacobG111 Nov 6, 2024
0a345d9
redid sch and layout w/ reverse polarity protection on HV and LV inpu…
JacobG111 Nov 10, 2024
74cf8a7
try 2
JacobG111 Nov 10, 2024
9a58508
updated sch explinations with new additions from today's workday
JacobG111 Nov 10, 2024
19fa866
fixed pmos orientation on LV reverse polarity protection, was s and d…
JacobG111 Nov 10, 2024
a0f2519
HV Layout w/ components on the back
JacobG111 Nov 11, 2024
03d07ed
components places on both sides of the board for HV and LV sides, rea…
JacobG111 Nov 13, 2024
7612e1a
sch done for workday 11/16/2024
JacobG111 Nov 16, 2024
c05ad5c
layout and sch ready for review (isolated DCDC convertor version)
JacobG111 Nov 19, 2024
1555c41
again
JacobG111 Nov 19, 2024
abfa3a3
added silkscreen labels to HV 1x3 connector
JacobG111 Nov 19, 2024
575500c
finished for review
JacobG111 Nov 23, 2024
1a9d4d7
fixed incorrect pmos pinout
JacobG111 Nov 23, 2024
bf43124
pretty sch changxu approved
JacobG111 Dec 6, 2024
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21,872 changes: 16,272 additions & 5,600 deletions ActivePrecharge.kicad_pcb

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6 changes: 3 additions & 3 deletions ActivePrecharge.kicad_prl
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
{
"board": {
"active_layer": 37,
"active_layer_preset": "All Layers",
"active_layer": 31,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
Expand Down Expand Up @@ -64,7 +64,7 @@
39,
40
],
"visible_layers": "fffffff_ffffffff",
"visible_layers": "ffcffff_ffffffff",
"zone_display_mode": 0
},
"git": {
Expand Down
29 changes: 24 additions & 5 deletions ActivePrecharge.kicad_pro
Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,8 @@
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 0.6,
"width": 1.625
"height": 3.0,
"width": 3.0
},
"silk_line_width": 0.1,
"silk_text_italic": false,
Expand All @@ -51,7 +51,13 @@
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
Expand Down Expand Up @@ -171,7 +177,11 @@
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"track_widths": [
0.0,
0.4,
1.0
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
Expand All @@ -198,7 +208,16 @@
"spacing": 0.6
}
},
"via_dimensions": [],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.8,
"drill": 0.4
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
Expand Down
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